公开(公告)号：US09570429B2

公开(公告)日：2017-02-14

申请号：US14694868

申请日：2015-04-23

申请人： Shanghai Lexvu Opto Microelectronics Technology Co., Ltd.

发明人： Jianhong Mao ,  Fengqin Han ,  Zhiwei Wang ,  Wenfen Chang

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/66

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/811 ,  H01L2224/83121 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2224/92 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L21/56 ,  H01L21/78 ,  H01L21/304

摘要： The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.

摘要翻译： 本发明提供了一种制造3D堆叠IC SiP的方法，其包括：提供第一半导体晶片，其具有形成在其上的多个第一裸片，每个具有第一引线键合焊盘和第一介电层，第一半导体晶片的至少一部分 引线接合焊盘不被第一介电层覆盖并构成第一裸片的暴露区域; 提供多个第二管芯，每个第二管芯具有第二引线接合焊盘和第二介电层，第二引线接合焊盘的至少一部分不被第二介电层覆盖，并且构成尺寸不同的第二裸片的暴露区域 从第一个死亡的; 将所述第二管芯与所述第一管芯对准并且将所述第二介电层接合到所述第一介电层; 电镀与第二模具结合的第一半导体晶片。

公开(公告)号：US09570350B2

公开(公告)日：2017-02-14

申请号：US14789908

申请日：2015-07-01

申请人： Micron Technology, Inc.

发明人： Mark E. Tuttle

IPC分类号： H01L21/768 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L21/76898 ,  H01L21/76895 ,  H01L23/552 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599

摘要： Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.

摘要翻译： 具有互连和导电背板的微特征工件以及相关联的系统和方法在本文中公开。 一种这样的器件包括具有集成电路和电耦合到集成电路的端子的半导体衬底。 该器件还包括延伸穿过半导体衬底的至少一部分并电耦合到相应端子的导电互连。 该器件还包括导电底板组件，其在半导体衬底的背面具有导电层。 一个或多个互连件在半导体衬底的背面电耦合到导电层。

公开(公告)号：US09564414B2

公开(公告)日：2017-02-07

申请号：US14746425

申请日：2015-06-22

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist ,  Gaius Gillman Fountain, Jr.

IPC分类号： H01L21/58 ,  H01L21/304 ,  H01L23/00 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L21/822 ,  H01L23/13 ,  H01L23/36 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L27/06 ,  H01L21/762 ,  H01L21/18 ,  H01L23/552 ,  H01L25/18 ,  H01L27/146

CPC分类号： H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

摘要翻译： 一种器件集成方法和集成器件。 该方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。 元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。 第二热扩散基板可以结合到半导体器件的其余部分。 互连可以通过第一或第二基底进行。 该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。 具有多个接触结构的导体阵列可以形成在半导体器件的暴露表面上，可以通过半导体器件到器件区域形成通孔，并且可以在所述器件区域和所述接触结构之间形成互连。

公开(公告)号：US09560773B2

公开(公告)日：2017-01-31

申请号：US14809117

申请日：2015-07-24

申请人： Tessera, Inc.

发明人： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC分类号： H05K1/03 ,  H05K1/09 ,  H05K3/40 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

摘要： An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, phosphorus, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent decreases throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer.

摘要翻译： 电连接结构包括具有选自硼，碳，磷和钨的次要成分的可变组成镍合金层，其中至少在一部分导电基底上，次要成分的浓度全部降低 该可变组成镍合金层在从可变组成镍合金层的底面到可变组成镍合金层的顶表面的方向上。

公开(公告)号：US20170005089A1

公开(公告)日：2017-01-05

申请号：US15265940

申请日：2016-09-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L21/28 ,  H02M3/155 ,  H01L29/49 ,  H01L29/423 ,  H02M7/00 ,  H01L29/66 ,  H01L29/45

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US09524929B2

公开(公告)日：2016-12-20

申请号：US14499181

申请日：2014-09-28

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Kwang Soo Kim ,  Joon Seok Chae ,  Suk Ho Lee

IPC分类号： H01L23/495 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L23/433 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/5384 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/293 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/32257 ,  H01L2224/35847 ,  H01L2224/37005 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40105 ,  H01L2224/40137 ,  H01L2224/40227 ,  H01L2224/40499 ,  H01L2224/40991 ,  H01L2224/40993 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/83136 ,  H01L2224/83139 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2224/84007 ,  H01L2224/84136 ,  H01L2224/84138 ,  H01L2224/84815 ,  H01L2224/92157 ,  H01L2224/92165 ,  H01L2224/92166 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/84

摘要： There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space.

摘要翻译： 提供了一种半导体模块封装，包括：通过在其上安装一个或多个第一半导体器件而形成的基底基板; 引线框架，形成在所述第一半导体器件的顶表面上，并且具有形成为用于注入焊膏的入口; 以及插入在第一半导体器件和引线框架之间的空间以形成分离空​​间，其中焊膏填充在分离空间中。

公开(公告)号：US09515019B2

公开(公告)日：2016-12-06

申请号：US15099574

申请日：2016-04-14

申请人： Renesas Electronics Corporation

发明人： Takahiro Hayashi ,  Shunsuke Toyoshima ,  Kazuo Sakamoto ,  Naozumi Morino ,  Kazuo Tanaka

IPC分类号： H01L29/74 ,  H01L23/50 ,  H01L23/498 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L23/49844 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L27/0255 ,  H01L27/092 ,  H01L2224/02166 ,  H01L2224/05025 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/06102 ,  H01L2224/06133 ,  H01L2224/06143 ,  H01L2224/06153 ,  H01L2224/06163 ,  H01L2224/49105 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

摘要翻译： 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。

公开(公告)号：US09508665B2

公开(公告)日：2016-11-29

申请号：US12831919

申请日：2010-07-07

申请人： Eric Beyne ,  Paresh Limaye

发明人： Eric Beyne ,  Paresh Limaye

IPC分类号： H01L21/30 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion.

摘要翻译： 公开了一种用于插入接合的方法和由此获得的器件。 一方面，该装置包括具有前主表面和在前主表面处的至少一个突起的第一基底。 该装置包括具有前主表面和从前主表面延伸到第二基板的至少一个孔的第二基板。 将第一基板的突起插入第二基板的孔中。 孔形成为宽度在深度方向上减小的形状，并且其中孔的至少一部分的宽度小于在其金属部分的位置处的突起的宽度。 突起在其插入孔期间变形，以在孔的一部分和金属部分之间形成结合。

公开(公告)号：US20160343764A1

公开(公告)日：2016-11-24

申请号：US15230281

申请日：2016-08-05

申请人： Sony Corporation

发明人： Hiroshi Takahashi ,  Taku Umebayashi

IPC分类号： H01L27/146

CPC分类号： H01L27/14636 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02325 ,  H01L31/18 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2224/45099

摘要： A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

摘要翻译： 一种半导体器件，具有在其一侧包括第一布线层的第一半导体部分; 其一侧包括第二布线层的第二半导体部分，所述第一和第二半导体部分与所述第一和第二半导体部分的相应的第一和第二布线层侧面相互固定在一起; 导电材料，其延伸穿过所述第一半导体部分到所述第二半导体部分的所述第二布线层，并且所述第一和第二布线层与所述第二半导体部分电连通; 以及除了通过第一半导体部分延伸到第二布线层的导电材料的开口以外的开口。

公开(公告)号：US09496237B2

公开(公告)日：2016-11-15

申请号：US14715778

申请日：2015-05-19

申请人： Infineon Technologies AG

发明人： Gottfried Beer ,  Raimund Foerg ,  Juergen Hoegerl

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/48

CPC分类号： H01L24/14 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2224/03464

摘要： A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable.

摘要翻译： 半导体器件包括半导体芯片和设置在半导体芯片的主面上的多个电接触焊盘，其中电接触焊盘各自包括层堆叠，每个层堆叠具有一层且相同的层数，并且其中 电接触焊盘都是可焊接和可焊接的。