公开(公告)号：US09570429B2

公开(公告)日：2017-02-14

申请号：US14694868

申请日：2015-04-23

申请人： Shanghai Lexvu Opto Microelectronics Technology Co., Ltd.

发明人： Jianhong Mao ,  Fengqin Han ,  Zhiwei Wang ,  Wenfen Chang

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/66

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/811 ,  H01L2224/83121 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2224/92 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L21/56 ,  H01L21/78 ,  H01L21/304

摘要： The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.

摘要翻译： 本发明提供了一种制造3D堆叠IC SiP的方法，其包括：提供第一半导体晶片，其具有形成在其上的多个第一裸片，每个具有第一引线键合焊盘和第一介电层，第一半导体晶片的至少一部分 引线接合焊盘不被第一介电层覆盖并构成第一裸片的暴露区域; 提供多个第二管芯，每个第二管芯具有第二引线接合焊盘和第二介电层，第二引线接合焊盘的至少一部分不被第二介电层覆盖，并且构成尺寸不同的第二裸片的暴露区域 从第一个死亡的; 将所述第二管芯与所述第一管芯对准并且将所述第二介电层接合到所述第一介电层; 电镀与第二模具结合的第一半导体晶片。