摘要:
A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.
摘要:
There are provided a solder joint structure, a power module using the joint structure, a power module substrate with a heat sink and a method of manufacturing the same, as well as a solder base layer forming paste which is disposed and fired on a metal member to thereby react with an oxide film generated on the surface of the metal member and form the solder base layer on the metal member, capable of suppressing the occurrence of waviness and wrinkles on the surface of the metal member even at the time of loading the power cycle and heat cycle and improving the joint reliability with a joint member.
摘要:
A light-emitting device assembly includes a plurality of light-emitting devices, the plurality of light-emitting devices being provided continuously, the plurality of light-emitting devices each including a substrate, an optical semiconductor element mounted on the surface of the substrate, an encapsulating layer formed on the substrate surface to encapsulate the optical semiconductor element, and an electrode formed on the substrate surface so as to be electrically connected to the optical semiconductor element. The substrate has a fragile region formed to partition off the light-emitting devices that are disposed next to each other.
摘要:
Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.
摘要:
A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess.
摘要:
A semiconductor package includes a package substrate, a first semiconductor chip having a plurality of first connection terminals disposed on a bottom surface thereof, and a second semiconductor chip having a plurality of second connection terminals disposed on a top surface thereof. The first semiconductor chip is stacked on the package substrate so that a first group of connection terminals among the plurality of first connection terminals are combined with the package substrate. The second semiconductor chip is disposed so that the plurality of second connection terminals are combined with a second group of connection terminals among the plurality of first connection terminals.
摘要:
Disclosed herein is a contact pin including: a deformation part elastically deformed; connection parts coupled to both ends of the deformation part; and contact parts coupled to the connection parts coupled to both ends of the deformation part, respectively, and having one end coupled to the connection part and the other end.
摘要:
In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer.
摘要:
A method of manufacturing a connection structure which includes a wiring substrate, a first electronic component that is flip-chip mounted on the front surface thereof, and a second electronic component that is flip-chip mounted on the rear surface. The method includes the steps of: temporarily mounting the first electronic component on the front surface of the wiring substrate with a first adhesive film disposed therebetween; temporarily mounting the second electronic component on the rear surface of the wiring substrate with a second adhesive film disposed therebetween, placing, on a pressure bonding receiving base, the wiring substrate on which the first electronic component and the second electronic component are temporarily mounted; and mounting the first electronic component and the second electronic component at a time onto the respective front and rear surfaces of the wiring substrate.
摘要:
One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.