公开(公告)号：US20150008445A1

公开(公告)日：2015-01-08

申请号：US14496140

申请日：2014-09-25

Applicant: International Rectifier Corporation

Inventor： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC: H01L25/07 ,  H01L29/16 ,  H01L29/772 ,  H01L23/00 ,  H01L29/20

CPC classification number: H01L25/074 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/69 ,  H01L24/72 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/772 ,  H01L29/778 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract translation: 一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。 封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。 封装的第三端子耦合到FET的源极。 以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

公开(公告)号：US09312245B2

公开(公告)日：2016-04-12

申请号：US14496140

申请日：2014-09-25

Applicant: International Rectifier Corporation

Inventor： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC: H01L25/07 ,  H01L27/20 ,  H01L23/495 ,  H01L29/20 ,  H01L29/16 ,  H01L29/772 ,  H01L23/00 ,  H01L29/778

CPC classification number: H01L25/074 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/69 ,  H01L24/72 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/772 ,  H01L29/778 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract translation: 一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。 封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。 封装的第三端子耦合到FET的源极。 以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。