公开(公告)号：US20070207605A1

公开(公告)日：2007-09-06

申请号：US11370387

申请日：2006-03-06

Applicant: Hei Shiu ,  On Chau ,  Gor Lai ,  Heng Yip ,  Thoon Chang ,  Lan Tan

Inventor： Hei Shiu ,  On Chau ,  Gor Lai ,  Heng Yip ,  Thoon Chang ,  Lan Tan

IPC: H01L21/44

CPC classification number: H05K3/4015 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11312 ,  H01L2224/1134 ,  H01L2224/118 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13144 ,  H01L2224/13194 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/3457 ,  H05K2201/0367 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81805

Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Abstract translation: 用于在衬底上形成增强互连或凸起的方法包括首先在衬底上形成支撑结构。 然后在支撑结构周围形成基本上填充的胶囊，以形成互连。 互连可以达到高达300微米的高度。

公开(公告)号：US20070123020A1

公开(公告)日：2007-05-31

申请号：US11531437

申请日：2006-09-13

Applicant: Gotthard Jungnickel ,  Alexander Platz ,  Frank Kuechenmeister

Inventor： Gotthard Jungnickel ,  Alexander Platz ,  Frank Kuechenmeister

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3457 ,  H05K3/3494 ,  H05K2203/0315 ,  H05K2203/043 ,  H05K2203/086 ,  H01L2924/00014

Abstract: By controlling the cooling rate during the oxidation process for forming an oxide layer on solder balls and by selecting an elevated temperature as an initial temperature of the oxidation process, a reliable yet easily removable oxide layer may be obtained. Consequently, yield losses during the flip chip assembly process may be significantly reduced.

Abstract translation: 通过控制用于在焊球上形成氧化物层的氧化过程中的冷却速度，并且通过选择升高的温度作为氧化工艺的初始温度，可以获得可靠且容易移除的氧化物层。 因此，倒装芯片组装过程中的屈服损失可能会显着降低。

公开(公告)号：US09711472B2

公开(公告)日：2017-07-18

申请号：US14451271

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

公开(公告)号：US09324557B2

公开(公告)日：2016-04-26

申请号：US14259530

申请日：2014-04-23

Applicant: LSI Corporation

Inventor： Steven D. Cate ,  John W. Osenbach

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/00 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/37 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/206 ,  H01L2224/03

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract translation: 一种在倒装芯片上形成金属柱的工艺。 支柱以及一层焊料将用于将器件上的管芯焊盘与衬底上相应的衬底焊盘接合。 在器件上沉积光致抗蚀剂，并且通过在光致抗蚀剂中形成第一直径的开口来暴露器件上的第一组裸片焊盘。 通过将金属电镀到暴露的裸片上而形成第一直径的支柱。 然后沉积在第一光致抗蚀剂上的第二光致抗蚀剂覆盖第一直径的柱。 在第一和第二光致抗蚀剂中形成第二直径的开口以暴露第二组裸片。 通过将金属电镀在暴露的裸片上形成第二直径的支柱。 然后将光致抗蚀剂与用作电镀工艺的一部分的器件上的导电层一起除去。

公开(公告)号：US09184143B2

公开(公告)日：2015-11-10

申请号：US14098218

申请日：2013-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Chun Miao ,  Shih-Wei Liang ,  Kai-Chiang Wu ,  Yen-Ping Wang

IPC: H01L23/00

CPC classification number: H01L23/564 ,  H01L23/16 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/03828 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2224/81 ,  H01L2224/03

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.

Abstract translation: 提供了具有半导体衬底的半导体器件。 半导体器件在半导体衬底上具有金属结构。 金属结构构造成接收凸起。 半导体器件还在半导体衬底和金属结构之间具有导电迹线。 导电迹线被配置为连接到电源。 当来自电源的电流通过导电迹线时，在导电迹线处产生电磁场。 凸起的位置响应于电磁场而被调节。

公开(公告)号：US20150255406A1

公开(公告)日：2015-09-10

申请号：US14201253

申请日：2014-03-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chun Miao ,  Shih-Wei Liang ,  Kai-Chiang Wu

IPC: H01L23/00 ,  H01L23/16

CPC classification number: H01L23/564 ,  H01L23/16 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/03828 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2224/81 ,  H01L2224/03

Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Abstract translation: 集成电路结构包括衬底，衬底上的金属焊盘，具有在金属焊盘上方的部分的钝化层以及钝化层上的聚合物层。 后钝化互连（PPI）具有聚合物层上的一部分，其中PPI电耦合到金属焊盘。 所述集成电路结构还包括在所述PPI的一部分上方并电耦合的第一焊料区域，与所述第一焊料区域相邻的第二焊料区域，所述第一焊料区域的表面上的第一涂覆材料和 第二焊料区域的表面。 第一涂料和第二涂料分别围绕第一焊料区域和第二焊料区域。 第一涂层材料与第二涂层材料间隔开。

公开(公告)号：US20130292820A1

公开(公告)日：2013-11-07

申请号：US13718311

申请日：2012-12-18

Applicant: SK HYNIX INC.

Inventor： Tae Min KANG

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/48 ,  H01L21/768 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05026 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked.

Abstract translation: 提供电子设备包装和相关方法。 电子器件封装包括具有设置在其上的第一接触部分的第一基板，具有连接到第一接触部分的第一接触表面的凸块和与第一接触表面相对设置的第二接触表面，以及缓冲弹簧垫部分 第一基板的第一接触部分和凸块的第一接触表面。 缓冲弹簧垫部分包括堆叠的至少两个不同的导电材料层。

公开(公告)号：US20120286423A1

公开(公告)日：2012-11-15

申请号：US13556016

申请日：2012-07-23

Applicant: Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

Inventor： Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

IPC: H01L23/498

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11416 ,  H01L2224/11422 ,  H01L2224/11424 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/132 ,  H01L2224/13211 ,  H01L2224/13339 ,  H01L2224/13562 ,  H01L2224/13584 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/1379 ,  H01L2224/13794 ,  H01L2224/13809 ,  H01L2224/13813 ,  H01L2224/13817 ,  H01L2224/13818 ,  H01L2224/1382 ,  H01L2224/13849 ,  H01L2224/13855 ,  H01L2224/13857 ,  H01L2224/1386 ,  H01L2224/13866 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2225/06513 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

公开(公告)号：US07494924B2

公开(公告)日：2009-02-24

申请号：US11370387

申请日：2006-03-06

Applicant: Hei Ming Shiu ,  On Lok Chau ,  Gor Amie Lai ,  Heng Keong Yip ,  Thoon Khin Chang ,  Lan Chu Tan

Inventor： Hei Ming Shiu ,  On Lok Chau ,  Gor Amie Lai ,  Heng Keong Yip ,  Thoon Khin Chang ,  Lan Chu Tan

IPC: H01L21/44

CPC classification number: H05K3/4015 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11312 ,  H01L2224/1134 ,  H01L2224/118 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13144 ,  H01L2224/13194 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/3457 ,  H05K2201/0367 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81805

Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Abstract translation: 用于在衬底上形成增强互连或凸起的方法包括首先在衬底上形成支撑结构。 然后在支撑结构周围形成基本上填充的胶囊，以形成互连。 互连可以达到高达300微米的高度。

公开(公告)号：US20160322273A1

公开(公告)日：2016-11-03

申请号：US14697937

申请日：2015-04-28

Applicant: NXP B.V.

Inventor： Chi-Feng Wu ,  Ting-Fong Bastiaan Simon Dai ,  Chyi Keh Chern

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L24/14 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/118 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/3511

Abstract: Consistent with an example embodiment, a WLCSP (wafer-level chip-scale package) device may be encapsulating in a six-sided protection envelope. The envelope is a molding compound or other resilient material. The encapsulated WLCSP device is protected from handling damage during assembly into the end user's system.

Abstract translation: 与示例实施例一致，WLCSP（晶片级芯片级封装）器件可以封装在六边保护封套中。 外壳是模塑料或其他弹性材料。 封装的WLCSP器件在组装到最终用户的系统中时不受处理损坏。