公开(公告)号：US09406603B2

公开(公告)日：2016-08-02

申请号：US14275137

申请日：2014-05-12

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tatsuo Nishizawa ,  Shinji Tada ,  Yoshito Kinoshita ,  Yoshinari Ikeda ,  Eiji Mochizuki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/522 ,  H01L25/07 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433 ,  H01L21/48 ,  H01L21/768 ,  H01L23/24

CPC分类号： H01L23/5226 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/16235 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8184 ,  H01L2224/81898 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.

摘要翻译： 公开了半导体器件，其中植入板和半导体安装板的半导体元件通过植入针接合并电连接，并且可以以高生产率制造。 植入针通过压配合到植入针的另一端的圆柱形端子与半导体元件和/或半导体安装板的电路图案接合。 每个植入销的压入深度L2可调整到相应的圆柱形端子中，使得相互压配合的植入销和圆柱形端子的总长度与半导体元件和/或 电路图案在半导体安装板和植入板上。

公开(公告)号：US09406598B2

公开(公告)日：2016-08-02

申请号：US14319678

申请日：2014-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Chao Mao ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC分类号： H01L29/40 ,  H01L23/498 ,  H01L23/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/48 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

摘要： An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.

摘要翻译： 一个实施方案是包括半导体管芯，半导体管芯的第一侧上的粘合剂层和围绕半导体管芯和粘合剂层的模制化合物的器件，其中模塑料与粘合剂层处于相同的水平。 该器件还包括电耦合到半导体管芯的第二侧的第一钝化后互连（PPI）和电耦合到第一PPI的第一连接器，其中第一连接器在模制化合物上方并对齐。

公开(公告)号：US09393645B2

公开(公告)日：2016-07-19

申请号：US13700294

申请日：2011-07-28

申请人： Takuto Yamaguchi ,  Masahide Okamoto ,  Osamu Ikeda ,  Hiromitsu Kuroda ,  Kazuma Kuroki ,  Shohei Hata ,  Yuichi Oda

发明人： Takuto Yamaguchi ,  Masahide Okamoto ,  Osamu Ikeda ,  Hiromitsu Kuroda ,  Kazuma Kuroki ,  Shohei Hata ,  Yuichi Oda

IPC分类号： B21B3/00 ,  B23K35/00 ,  B23K35/02 ,  B23K1/00 ,  B23K35/28 ,  B23K35/30 ,  B23K35/38 ,  B32B15/01 ,  C22C5/02 ,  C22C9/00 ,  C22F1/00 ,  C22F1/04 ,  C22F1/08 ,  C22F1/16 ,  H01L21/50 ,  H01L23/06 ,  H01L23/10 ,  H01L23/373 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC分类号： B23K35/0238 ,  B21B3/00 ,  B23K1/0016 ,  B23K35/282 ,  B23K35/286 ,  B23K35/302 ,  B23K35/38 ,  B23K35/383 ,  B23K2101/40 ,  B32B15/017 ,  B32B15/018 ,  C22C5/02 ,  C22C9/00 ,  C22F1/00 ,  C22F1/04 ,  C22F1/08 ,  C22F1/165 ,  H01L21/50 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/2784 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2224/8382 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/013 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  Y10T428/12708 ,  Y10T428/12736 ,  Y10T428/12792 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/83205

摘要： The disclosed junction material, manufacturing method thereof, and manufacturing method of junction structure utilize lead-free materials and ensure a high reliability of the junction between a semiconductor element and a frame or substrate, or, between a metal plate and another metal plate. For junctions between a semiconductor element and a frame or substrate, by using as the JUNCTION MATERIAL a laminate material comprising a Zn-based metallic layer (101), Al-based metallic layers (102a, 102b) on both sides thereof, and X-based metallic layers (103a, 103b) (X=Cu, Au, Ag or Sn) on the outside of both the Al-based metallic layers (102a, 102b), even in an oxygen-rich environment, the superficial X-based metallic layers protect the Zn and Al from oxidation until said junction material melts, preserving the wettability and bondability of said junction material as solder and securing the high reliability of the junction.

摘要翻译： 所公开的连接材料，其制造方法和接合结构的制造方法利用无铅材料，并确保半导体元件与框架或基板之间或者金属板与另一金属板之间的接合部的高可靠性。 对于半导体元件和框架或基板之间的接合，通过使用作为连接材料的层叠材料，其包含Zn基金属层（101），其两侧上的Al基金属层（102a，102b）和X- 即使在富含氧的环境下，Al基金属层（102a，102b）外侧的金属基金属层（103a，103b）（X = Cu，Au，Ag或Sn），表面的X系金属 层保护Zn和Al免于氧化，直到所述接合材料熔化，保持所述接合材料作为焊料的润湿性和粘合性，并确保接合部的高可靠性。

公开(公告)号：US09391021B2

公开(公告)日：2016-07-12

申请号：US12506278

申请日：2009-07-21

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L23/525 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/293 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

公开(公告)号：US20160195432A1

公开(公告)日：2016-07-07

申请号：US15072100

申请日：2016-03-16

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Jiho JOO

IPC分类号： G01J1/44 ,  H05K1/11 ,  H05K1/18

CPC分类号： G01J1/44 ,  G01J2001/444 ,  G02B6/4279 ,  H01L23/13 ,  H01L24/48 ,  H01L31/02016 ,  H01L31/16 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15173 ,  H01L2924/15787 ,  H05K1/0206 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/181 ,  H05K3/3431 ,  H05K3/4697 ,  H05K2201/0191 ,  H05K2201/09845 ,  H05K2201/10121 ,  H05K2201/10189 ,  H05K2201/10272 ,  H05K2201/10287 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/45099

摘要： Provided is a optical transceiver module. The optical transceiver module includes a printed circuit board (PCB) configured to include a plurality of dielectric layers and a plurality of metal layers stacked alternately, a photodetector disposed on the PCB to convert an optical signal into an electrical signal, a compensator disposed on one side on the PCB and including a first transmission line that delivers an electrical signal, a power supply line configured to supply power to the photodetector, and a first high frequency connector configured to connect to the first transmission line to deliver the electrical signal, wherein the PCB includes a plurality of vias that electrically connect the plurality of dielectric layers and the plurality of metal layers, and the compensator protrudes from the PCB to compensate for a height difference from the photodetector.

摘要翻译： 提供了一种光收发模块。 光收发器模块包括：印刷电路板（PCB），其被配置为包括多个电介质层和交替堆叠的多个金属层，设置在PCB上以将光信号转换成电信号的光电检测器，设置在一个上的补偿器 并且包括传送电信号的第一传输线，被配置为向光电检测器供电的电源线以及被配置为连接到第一传输线以传送电信号的第一高频连接器，其中， PCB包括多个通孔，其电连接多个电介质层和多个金属层，并且补偿器从PCB突出以补偿与光电检测器的高度差。

公开(公告)号：US20160194199A1

公开(公告)日：2016-07-07

申请号：US15067043

申请日：2016-03-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Ying Chen ,  Yi Hsun Chiu ,  Ching-Hou Su ,  Chyi-Tsong Ni

IPC分类号： B81C1/00

CPC分类号： B81C1/00825 ,  B81B2207/03 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/036 ,  B81C2203/054 ,  H01L21/50 ,  H01L22/32 ,  H01L23/10 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/32268 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2224/83

摘要： A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

摘要翻译： 晶片密封环可以形成在第一和/或第二晶片上。 第一和/或第二晶片中的一个或两个可以具有在其上形成的一个或多个模具。 晶片密封环可以形成为围绕相应晶片的管芯。 可以在一个或多个管芯周围形成一个或多个管芯密封环。 晶片密封环可以形成为可以大致等于形成在第一和/或第二晶片上的一个或多个模具密封环的高度的高度。 可以形成晶片密封环以提供共晶或熔接工艺。 第一和第二晶片可以结合在一起以在第一和第二晶片之间形成密封环结构。 密封环结构可以在第一和第二晶片之间提供密封。

公开(公告)号：US09379083B2

公开(公告)日：2016-06-28

申请号：US14455184

申请日：2014-08-08

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yuji Iizuka ,  Masafumi Horio ,  Hideyo Nakamura

IPC分类号： H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H02M7/00 ,  H01L25/07 ,  H01L23/31 ,  H01L23/34 ,  H01L29/66 ,  H01L23/498 ,  H01L23/051 ,  H01L25/11 ,  H01L23/538

CPC分类号： H01L24/80 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/02 ,  H01L25/072 ,  H01L25/115 ,  H01L25/117 ,  H01L25/18 ,  H01L29/66325 ,  H01L2224/06 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H02M7/003 ,  H05K1/0263 ,  H05K2201/10166 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is a composite module in which three power semiconductor modules are arranged at a predetermined interval in the same plane and pin-shaped conductors that are drawn from the power semiconductor modules to the outside are connected to three main terminal plates such that they are integrated with each other. When the entire composite module is accommodated in a protective case and a radiation fin is provided, bolts are inserted into through holes to fix the protective case to the radiation fin. In this way, it is possible to accommodate the composite module in the protective case while reliably bringing the bottom of an insulating substrate into close contact with the radiation fin.

摘要翻译： 半导体器件是复合模块，其中三个功率半导体模块以相同的平面以预定的间隔布置，并且从功率半导体模块到外部的引脚形状的导体连接到三个主端子板，使得它们是 相互融合。 当整个复合模块被容纳在保护壳体中并且设置有辐射翅片时，将螺栓插入通孔中以将保护壳固定到辐射翅片上。 以这种方式，可以将复合模块容纳在保护壳体中，同时可靠地使绝缘基板的底部与辐射翅片紧密接触。

公开(公告)号：US09378986B2

公开(公告)日：2016-06-28

申请号：US14511353

申请日：2014-10-10

申请人： Point Engineering Co., Ltd.

发明人： Bum Mo Ahn ,  Ki Myung Nam ,  Seung Ho Park

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L21/563 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/11 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/1183 ,  H01L2224/13144 ,  H01L2224/291 ,  H01L2224/32013 ,  H01L2224/32227 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/92227 ,  H01L2924/12041 ,  H01L2924/15156 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.

摘要翻译： 提供了一种安装芯片的方法。 该方法包括：在衬底的内部方向上凹入地形成的空腔的一个表面上形成凸块; 执行压印工艺以平坦化凸块的表面; 在经过压印加工的凸块上涂覆焊料; 并且通过熔化焊料材料来接合芯片和凸块，其中在芯片的底部上形成电极部分或金属部分。 对于根据本发明的金属基板，其中包括垂直绝缘层，由于芯片的电极部分和基板的电极部分必须电连接，金属基板被接合到芯片的电极部分 使用另外形成在金属基板上的凸块，使得芯片中产生的热量可以快速转移到基板，并且可以降低芯片的结温，从而提高光效率。 此外，通过使用焊料材料密封芯片的接合部分，可以防止由于焊料材料之间的热膨胀系数的差异导致的破裂。 此外，由于通过阻挡与外部的接触来防止接合部的氧化，所以可以进行芯片封装处理，而不需要在安装芯片的内部空间中填充惰性气体的附加处理。

公开(公告)号：US20160181171A1

公开(公告)日：2016-06-23

申请号：US14600733

申请日：2015-01-20

申请人： Global Circuit Innovations Incorporated

发明人： Erick Merle Spory

IPC分类号： H01L23/20 ,  H01L21/48 ,  H01L23/498 ,  H01L23/495 ,  H01L23/04 ,  H01L23/00 ,  H01L23/26

CPC分类号： H01L23/20 ,  H01L21/4803 ,  H01L21/4817 ,  H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/26 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49861 ,  H01L23/564 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24175 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/2731 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/82102 ,  H01L2224/82103 ,  H01L2224/82214 ,  H01L2224/82815 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3656 ,  H01L2924/3861 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00

摘要： A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads, and die attach adhesive for securing the die to the package base. the die includes a plurality of die pads. The die is secured to the base with the die attach adhesive. After the die is secured to the base, at least one of the plurality of die pads is electrically connected to at least one of the plurality of package leads with a printed bond connection. After printing the bond connection, the lid is sealed to the base.

摘要翻译： 提供封装的集成电路。 封装的集成电路包括管芯，包括基座，盖子和多个封装引线的封装以及用于将管芯固定到封装基座的管芯附着粘合剂。 管芯包括多个管芯焊盘。 模具用芯片附着粘合剂固定到基座上。 在芯片被固定到基座之后，多个裸片焊盘中的至少一个通过印刷的键合电连接到多个封装引线中的至少一个。 在打印粘合连接之后，将盖子密封到基座上。

公开(公告)号：US09362191B2

公开(公告)日：2016-06-07

申请号：US14013495

申请日：2013-08-29

申请人： Infineon Technologies Austria AG

发明人： Khalil Hosseini ,  Joachim Mahler ,  Ivan Nikitin

IPC分类号： H01L23/29 ,  H01L23/28 ,  H01L21/56 ,  H01L23/34 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49568 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/48247 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a carrier and a semiconductor chip disposed over the carrier. The semiconductor chip has a first surface and a second surface opposite to the first surface, wherein the second surface faces the carrier. Further, the semiconductor device includes a pre-encapsulant covering at least partially the second surface of the semiconductor chip and at least partially a side wall surface of the semiconductor chip. The pre-encapsulant has a thermal conductivity of equal to or greater than 10 W/(m·K) and a specific heat capacity of equal to or greater than 0.2 J/(g·K).

摘要翻译： 半导体器件包括载体和布置在载体上的半导体芯片。 半导体芯片具有与第一表面相对的第一表面和第二表面，其中第二表面面向载体。 此外，半导体器件包括至少部分地覆盖半导体芯片的第二表面和至少部分地覆盖半导体芯片的侧壁表面的预封装。 预封装具有等于或大于10W /（m·K）的热导率和等于或大于0.2J /（g·K）的比热容。