公开(公告)号：US09159720B2

公开(公告)日：2015-10-13

申请号：US13905425

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/02 ,  H01L27/06 ,  H01L23/00 ,  H01L49/02 ,  H01L23/495

CPC classification number: H01L23/49589 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L28/40 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85191 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip.

Abstract translation: 半导体模块包括半导体芯片和无源分立元件。 半导体芯片在其顶侧和/或背面上包括一个或多个触点，其在其二维范围内实质上完全占据了半导体芯片的顶侧和/或背面。 布置在封装中的被动元件堆叠在触点之一上。 无源部件的电极与触点之一电连接。 无源部件的对电极与半导体芯片的控制或信号电极或另一半导体芯片的电极可操作地连接。

公开(公告)号：US09159684B1

公开(公告)日：2015-10-13

申请号：US14246394

申请日：2014-04-07

Applicant: Maxim Integrated Products, Inc.

Inventor： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante Alvarado

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11914 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83907 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3025

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract translation: 描述了晶片级封装半导体器件。 在一个实现中，该装置包括设置在集成电路芯片上的一个或多个自组装的弹性引线。 每个弹性引线构造成从第一位置移动，其中弹性引线邻近芯片保持，第二位置，其中弹性引线远离芯片延伸以将芯片与印刷电路板互连。 当弹性引线处于第一位置时，提供防护件以保护弹性引线。 还可以设置一个或多个附接凸块以便于将装置附接到印刷电路板。

公开(公告)号：US09159638B2

公开(公告)日：2015-10-13

申请号：US13116201

申请日：2011-05-26

Applicant: Kuo-Chin Chang ,  Yuh Chern Shieh

Inventor： Kuo-Chin Chang ,  Yuh Chern Shieh

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76837 ,  H01L23/3171 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01327 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.

Abstract translation: 本发明涉及半导体器件的凸块结构。 半导体器件的示例性结构包括衬底; 衬底上的接触垫; 钝化层，其延伸在所述衬底上并且具有在所述接触焊盘上的第一宽度的开口; 开口内的导电通孔; 以及具有完全覆盖所述导电通孔的第二宽度的导电柱，其中所述第一宽度与所述第二宽度的比率为约0.15至0.55。

公开(公告)号：US09147637B2

公开(公告)日：2015-09-29

申请号：US13336248

申请日：2011-12-23

Applicant: Ralf Otremba ,  Roland Rupp ,  Daniel Domes

Inventor： Ralf Otremba ,  Roland Rupp ,  Daniel Domes

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/24 ,  H01L23/373 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/48 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37639 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/3766 ,  H01L2224/4005 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/4847 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48766 ,  H01L2224/48769 ,  H01L2224/48771 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/8382 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/8482 ,  H01L2224/8485 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01015 ,  H01L2924/20759

Abstract: A module includes a DCB substrate and a discrete device mounted on the DCB substrate, wherein the discrete device comprises a leadframe, a semiconductor chip mounted on the leadframe and an encapsulation material covering the semiconductor chip.

Abstract translation: 模块包括DCB衬底和安装在DCB衬底上的分立器件，其中分立器件包括引线框，安装在引线框上的半导体芯片和覆盖半导体芯片的封装材料。

公开(公告)号：US09112059B2

公开(公告)日：2015-08-18

申请号：US13349155

申请日：2012-01-12

Applicant: Tomohiro Uno ,  Keiichi Kimura ,  Shinichi Terashima ,  Takashi Yamada ,  Akihito Nishibayashi

Inventor： Tomohiro Uno ,  Keiichi Kimura ,  Shinichi Terashima ,  Takashi Yamada ,  Akihito Nishibayashi

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/85 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/4312 ,  H01L2224/4321 ,  H01L2224/43825 ,  H01L2224/43847 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/456 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/45671 ,  H01L2224/45673 ,  H01L2224/4568 ,  H01L2224/45684 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/78251 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85048 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/859 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01105 ,  H01L2924/01204 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/15747 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/3025 ,  H01L2924/3861 ,  H01L2924/01001 ,  H01L2924/01203 ,  H01L2924/01034 ,  H01L2924/01081 ,  H01L2924/20645 ,  H01L2924/20652 ,  H01L2924/20653 ,  H01L2924/00014 ,  H01L2924/20108 ,  H01L2224/45657 ,  H01L2224/45666 ,  H01L2924/01008 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2076 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/20654 ,  H01L2924/00 ,  H01L2224/45124 ,  H01L2924/013 ,  H01L2924/20751 ,  H01L2924/2075 ,  H01L2924/00013 ,  H01L2924/01049

Abstract: It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 μm in thickness.

Abstract translation: 本发明的目的是提供一种铜基接合线，其材料成本低，具有优异的球接合性，热循环试验或回流试验的可靠性以及储存寿命，使得能够使用的线材变薄 用于细间距连接。 接合线包括具有铜作为主要成分的芯材和设置在芯材上并且包含金属M和铜的外层，其中金属M与芯材料在组分和组成中的一种或两种中不同 。 外层的厚度为0.021〜0.12μm。

公开(公告)号：US09099345B2

公开(公告)日：2015-08-04

申请号：US13608555

申请日：2012-09-10

Applicant: Rey Alvarado ,  Tie Wang ,  Arkadii Samoilov

Inventor： Rey Alvarado ,  Tie Wang ,  Arkadii Samoilov

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05541 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/11424 ,  H01L2224/11602 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2224/11 ,  H01L2924/207 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract translation: WLP器件在铜柱式电路连接的顶部设置有凸缘形UBM或嵌入式部分焊球UBM。

公开(公告)号：US09064940B2

公开(公告)日：2015-06-23

申请号：US13732622

申请日：2013-01-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/6836 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13009 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/059 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Abstract translation: 提供一种半导体衬底，其具有穿过硅通孔和半导体衬底之间的气隙的通硅通孔。 部分地通过半导体衬底形成开口。 开口首先衬有第一衬里，然后开口填充有导电材料。 半导体衬底的背面变薄以露出第一衬垫，随后将其移除，并且在其位置形成形成有低k或超低k电介质的第二衬垫。

公开(公告)号：US09034751B2

公开(公告)日：2015-05-19

申请号：US14335660

申请日：2014-07-18

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Konrad Roesl ,  Oliver Eichinger

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/93 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/27426 ,  H01L2224/2745 ,  H01L2224/29018 ,  H01L2224/29019 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/8381 ,  H01L2224/83898 ,  H01L2224/83906 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2224/27 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

Abstract translation: 一种方法包括提供具有沉积在第一主表面上的第一主表面和焊料层的半导体芯片，其中焊料层的粗糙度至少为1μm。 将半导体芯片放置在载体上，半导体芯片的第一主表面面向载体。 将半导体芯片按第一主表面的表面积至少为1牛顿/千克的压力压在载体上，并将热量施加到焊料材料上。

公开(公告)号：US20150132940A1

公开(公告)日：2015-05-14

申请号：US14596851

申请日：2015-01-14

Applicant: Intel Corporation

Inventor： Madhav Datta ,  Dave Emory ,  Subhash M. Joshi ,  Susanne Menezes ,  Doowon Suh

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

Abstract translation: 本发明涉及一种用于电气装置的极限极限冶金堆，其包含设置在Ti粘附金属层上的至少一个铜层。 限流冶金叠层可阻止Sn向器件的上部金属化迁移。

公开(公告)号：US09027822B2

公开(公告)日：2015-05-12

申请号：US13822708

申请日：2011-08-25

Applicant: Daisuke Sakurai

Inventor： Daisuke Sakurai

IPC: B23K31/02 ,  B23K35/02 ,  B23K1/00 ,  B23K1/20 ,  B23K3/06 ,  H01L21/683 ,  H01L23/00 ,  H05K3/34

CPC classification number: B23K35/0244 ,  B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K1/206 ,  B23K3/0607 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11332 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K3/3478 ,  H05K3/3484 ,  H05K2201/0209 ,  H05K2203/0338 ,  H05K2203/0425 ,  H05K2203/043 ,  Y10T428/24372 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/0103

Abstract: An adhesive layer forming step of forming an adhesive layer on a surface of a substrate; a solder layer forming step of forming a solder layer on the adhesive layer by loading plural solder powders with in-between spaces; and a filler supplying step of supplying fillers to the in-between spaces of the solder powders that have been formed on the adhesive layer are included.

Abstract translation: 一种在基板的表面上形成粘合剂层的粘合剂层形成步骤; 焊料层形成步骤，通过在其间填充多个焊料粉末而在所述粘合剂层上形成焊料层; 并且包括向已经形成在粘合剂层上的焊料粉末的中间空间之间供给填料的填料供给步骤。