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公开(公告)号：US20120299161A1
公开(公告)日：2012-11-29
申请号：US13116201
申请日：2011-05-26
Applicant: Kuo-Chin CHANG , Yuh Chern SHIEH
Inventor： Kuo-Chin CHANG , Yuh Chern SHIEH
CPC classification number: H01L23/528 , H01L21/76802 , H01L21/76837 , H01L23/3171 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03472 , H01L2224/0391 , H01L2224/0401 , H01L2224/05012 , H01L2224/05016 , H01L2224/05026 , H01L2224/05147 , H01L2224/05568 , H01L2224/05571 , H01L2224/05647 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/13006 , H01L2224/13023 , H01L2224/13147 , H01L2924/00014 , H01L2924/01012 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/014 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.
Abstract translation: 本发明涉及半导体器件的凸块结构。 半导体器件的示例性结构包括衬底; 衬底上的接触垫; 钝化层，其延伸在所述衬底上并且具有在所述接触焊盘上的第一宽度的开口; 开口内的导电通孔; 以及具有完全覆盖所述导电通孔的第二宽度的导电柱，其中所述第一宽度与所述第二宽度的比率为约0.15至0.55。
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公开(公告)号：US09041223B2
公开(公告)日：2015-05-26
申请号：US13610050
申请日：2012-09-11
Applicant: Yuh Chern Shieh , Han-Ping Pu , Yu-Feng Chen , Tin-Hao Kuo
Inventor： Yuh Chern Shieh , Han-Ping Pu , Yu-Feng Chen , Tin-Hao Kuo
CPC classification number: H01L24/14 , H01L23/488 , H01L23/49811 , H01L23/49838 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/11849 , H01L2224/13005 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1405 , H01L2224/14131 , H01L2224/145 , H01L2224/16104 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81484 , H01L2224/81815 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/05552
Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.
Abstract translation: 描述了跟踪（BOT）结构。 BOT结构包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线。 BOT结构还包括具有细长金属凸块的第二工件，其中细长金属凸块具有第二轴线，其中第二轴线与第一轴线成非零角度。 BOT结构还包括金属凸块，其中金属凸块电连接金属迹线和细长金属凸块。 还描述了具有BOT结构的封装和形成BOT结构的方法。
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公开(公告)号：US09159638B2
公开(公告)日：2015-10-13
申请号：US13116201
申请日：2011-05-26
Applicant: Kuo-Chin Chang , Yuh Chern Shieh
Inventor： Kuo-Chin Chang , Yuh Chern Shieh
IPC: H01L23/528 , H01L23/31 , H01L23/00
CPC classification number: H01L23/528 , H01L21/76802 , H01L21/76837 , H01L23/3171 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03472 , H01L2224/0391 , H01L2224/0401 , H01L2224/05012 , H01L2224/05016 , H01L2224/05026 , H01L2224/05147 , H01L2224/05568 , H01L2224/05571 , H01L2224/05647 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/13006 , H01L2224/13023 , H01L2224/13147 , H01L2924/00014 , H01L2924/01012 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/014 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.
Abstract translation: 本发明涉及半导体器件的凸块结构。 半导体器件的示例性结构包括衬底; 衬底上的接触垫; 钝化层，其延伸在所述衬底上并且具有在所述接触焊盘上的第一宽度的开口; 开口内的导电通孔; 以及具有完全覆盖所述导电通孔的第二宽度的导电柱，其中所述第一宽度与所述第二宽度的比率为约0.15至0.55。
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公开(公告)号：US08970033B2
公开(公告)日：2015-03-03
申请号：US13035586
申请日：2011-02-25
Applicant: Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
Inventor： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L24/16 , H01L23/49816 , H01L23/49838 , H01L24/13 , H01L24/17 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16013 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
Abstract translation: 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。
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公开(公告)号：US20130001778A1
公开(公告)日：2013-01-03
申请号：US13610050
申请日：2012-09-11
Applicant: Yuh Chern SHIEH , Han-Ping PU , Yu-Feng CHEN , Tin-Hao KUO
Inventor： Yuh Chern SHIEH , Han-Ping PU , Yu-Feng CHEN , Tin-Hao KUO
IPC: H01L23/498 , H01L21/56
CPC classification number: H01L24/14 , H01L23/488 , H01L23/49811 , H01L23/49838 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/11849 , H01L2224/13005 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1405 , H01L2224/14131 , H01L2224/145 , H01L2224/16104 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81484 , H01L2224/81815 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/05552
Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.
Abstract translation: 描述了跟踪（BOT）结构。 BOT结构包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线。 BOT结构还包括具有细长金属凸块的第二工件，其中细长金属凸块具有第二轴线，其中第二轴线与第一轴线成非零角度。 BOT结构还包括金属凸块，其中金属凸块电连接金属迹线和细长金属凸块。 还描述了具有BOT结构的封装和形成BOT结构的方法。
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Patent Agency Ranking
公开(公告)号：US20120286417A1
公开(公告)日：2012-11-15
申请号：US13105360
申请日：2011-05-11
Applicant: Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
Inventor： Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
IPC: H01L23/485 , G06F17/50 , H01L21/58
CPC classification number: H01L23/562 , H01L23/3157 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15321 , H01L2924/3511 , H01L2924/00
Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.
Abstract translation: 一种方法包括确定集成电路（IC）封装设计的翘曲。 IC封装设计包括在第一主表面上具有顶部焊接掩模的基板和与第一主表面相对的第二主表面上的底部焊接掩模。 第一主表面上安装有IC芯片，顶部焊接掩模。 该设计被修改，包括修改由顶部焊接掩模和底部焊接掩模组成的组中的一个的平均厚度，以便减少翘曲。 根据改进的设计制造IC封装。
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公开(公告)号：US20120273934A1
公开(公告)日：2012-11-01
申请号：US13095185
申请日：2011-04-27
Applicant: Yuh Chern SHIEH , Han-Ping PU , Yu-Feng CHEN , Tin-Hao KUO
Inventor： Yuh Chern SHIEH , Han-Ping PU , Yu-Feng CHEN , Tin-Hao KUO
IPC: H01L23/498 , G06F17/50
CPC classification number: H01L24/14 , H01L23/488 , H01L23/49811 , H01L23/49838 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/11849 , H01L2224/13005 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1405 , H01L2224/14131 , H01L2224/145 , H01L2224/16104 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81484 , H01L2224/81815 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/05552
Abstract: The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.
Abstract translation: 凹凸跟踪（BOT）结构及其在芯片上的布局的实施例减少了金属焊盘上的电介质层和BOT结构的金属迹线上的应力。 通过将金属凸块的轴线定位成远离金属轨迹，可以减小应力，这可以降低金属迹线从基板和电介质层与金属垫分层的危险。 此外，金属焊盘和金属迹线上的电介质层的应力也可以通过将金属迹线的轴线朝向芯片的中心定向而减小。 结果，可以提高收率。
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公开(公告)号：US20120217632A1
公开(公告)日：2012-08-30
申请号：US13035586
申请日：2011-02-25
Applicant: Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
Inventor： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
IPC: H01L23/498
CPC classification number: H01L24/16 , H01L23/49816 , H01L23/49838 , H01L24/13 , H01L24/17 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16013 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
Abstract translation: 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。
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公开(公告)号：US08519535B2
公开(公告)日：2013-08-27
申请号：US13105360
申请日：2011-05-11
Applicant: Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
Inventor： Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
CPC classification number: H01L23/562 , H01L23/3157 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15321 , H01L2924/3511 , H01L2924/00
Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.
Abstract translation: 一种方法包括确定集成电路（IC）封装设计的翘曲。 IC封装设计包括在第一主表面上具有顶部焊接掩模的基板和与第一主表面相对的第二主表面上的底部焊接掩模。 第一主表面上安装有IC芯片，顶部焊接掩模。 该设计被修改，包括修改由顶部焊接掩模和底部焊接掩模组成的组中的一个的平均厚度，以便减少翘曲。 根据改进的设计制造IC封装。
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公开(公告)号：US08288871B1
公开(公告)日：2012-10-16
申请号：US13095185
申请日：2011-04-27
Applicant: Yuh Chern Shieh , Han-Ping Pu , Yu-Feng Chen , Tin-Hao Kuo
Inventor： Yuh Chern Shieh , Han-Ping Pu , Yu-Feng Chen , Tin-Hao Kuo
CPC classification number: H01L24/14 , H01L23/488 , H01L23/49811 , H01L23/49838 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/11849 , H01L2224/13005 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1405 , H01L2224/14131 , H01L2224/145 , H01L2224/16104 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81484 , H01L2224/81815 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/05552
Abstract: The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.
Abstract translation: 凹凸跟踪（BOT）结构及其在芯片上的布局的实施例减少了金属焊盘上的电介质层和BOT结构的金属迹线上的应力。 通过将金属凸块的轴线定位成远离金属轨迹，可以减小应力，这可以降低金属迹线从基板和电介质层与金属垫分层的危险。 此外，金属焊盘和金属迹线上的电介质层的应力也可以通过将金属迹线的轴线朝向芯片的中心定向而减小。 结果，可以提高收率。
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