Invention Application
- Patent Title: METHOD AND STRUCTURE FOR CONTROLLING PACKAGE WARPAGE
- Patent Title (中): 用于控制包装件的方法和结构
-
Application No.: US13105360Application Date: 2011-05-11
-
Publication No.: US20120286417A1Publication Date: 2012-11-15
- Inventor: Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
- Applicant: Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/485
- IPC: H01L23/485 ; G06F17/50 ; H01L21/58

Abstract:
A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.
Public/Granted literature
- US08519535B2 Method and structure for controlling package warpage Public/Granted day:2013-08-27
Information query
IPC分类: