公开(公告)号：US08976529B2

公开(公告)日：2015-03-10

申请号：US13007249

申请日：2011-01-14

Applicant: Wen-Yi Lin ,  Po-Yao Lin ,  Tsung-Shu Lin ,  Kuo-Chin Chang ,  Shou-Yi Wang

Inventor： Wen-Yi Lin ,  Po-Yao Lin ,  Tsung-Shu Lin ,  Kuo-Chin Chang ,  Shou-Yi Wang

IPC: H05K7/20 ,  H01L23/16 ,  H01L23/055 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/055 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.

Abstract translation: 在包装结构中，加强环在第一包装部件的顶表面上结合并结合。 第二包装部件在第一包装部件的顶部表面上结合并且被加强环环绕。 金属盖已经结合到加强环上。 金属盖具有通孔。

公开(公告)号：US20110057313A1

公开(公告)日：2011-03-10

申请号：US12899168

申请日：2010-10-06

Applicant: Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

Inventor： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

IPC: H01L23/498

CPC classification number: H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

Abstract translation: 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

公开(公告)号：US07662665B2

公开(公告)日：2010-02-16

申请号：US11655844

申请日：2007-01-22

Applicant: Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

Inventor： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

IPC: H01L21/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

Abstract translation: 提供一种制造半导体封装的方法。 在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。 提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。 半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并且与暴露的通孔塞的表面接触。 然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。 在多个通孔塞的相对端的表面上形成多个UBM层。 多个焊料凸起形成并安装在UBM层上。 提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。 多个焊球形成并安装在第二基板的第二表面上。 第三衬底安装到焊球。

公开(公告)号：US20080023850A1

公开(公告)日：2008-01-31

申请号：US11493375

申请日：2006-07-26

Applicant: Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

Inventor： Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC: H01L23/48

CPC classification number: H01L23/147 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract translation: 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装衬底优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。 硅基薄封装衬底可以用作半导体芯片的载体。

公开(公告)号：US20070069366A1

公开(公告)日：2007-03-29

申请号：US11237924

申请日：2005-09-29

Applicant: Kuo-Chin Chang ,  Ching-Yu Ni

Inventor： Kuo-Chin Chang ,  Ching-Yu Ni

IPC: H01L23/12

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/562 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/15311

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract translation: 提供了用于加强集成电路封装的约束加强件。 在一个实施例中，约束加强件包括用于结合到集成电路基板的刚性平面基座元件。 基座元件具有多个细长的支撑构件，并且基座元件具有用于围绕集成电路的开口。 基部元件和支撑构件由于至少集成电路和基板之间的热膨胀失配而减少翘曲。 在一个实施例中，细长支撑构件可从基座元件的角部拆卸。 在另一个实施例中，细长支撑构件具有用于附接和分离到基部元件的角部的装置。 在另一个实施例中，细长的支撑构件可从基部元件的中央部分的周围拆卸。 在另一个实施例中，细长的支撑构件具有用于附接和分离到基部元件的中部的装置。

公开(公告)号：US20060055032A1

公开(公告)日：2006-03-16

申请号：US10941586

申请日：2004-09-14

Applicant: Kuo-Chin Chang ,  Kuo-Ning Chiang

Inventor： Kuo-Chin Chang ,  Kuo-Ning Chiang

IPC: H01L23/48

CPC classification number: H05K3/3436 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/351 ,  H05K1/111 ,  H05K2201/0367 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05099

Abstract: A semiconductor assembly has solder bumps with increased reliability. One embodiment of an assembly comprises a first substrate having at least one conductive pad on its surface; a second substrate having at least one conductive pad on its surface; at least one conductive stud; and at least one solder bump in contact with the conductive pad on the first substrate, and in contact with the conductive pad of the second substrate, and formed around the at least one conductive stud. Methods for providing these assemblies are included.

Abstract translation: 半导体组件具有增加的可靠性的焊料凸块。 组件的一个实施例包括在其表面上具有至少一个导电垫的第一衬底; 第二基板，其表面上具有至少一个导电垫; 至少一个导电螺柱; 以及与所述第一基板上的所述导电焊盘接触并与所述第二基板的所述导电焊盘接触并且形成在所述至少一个导电螺柱周围的至少一个焊料凸块。 包括提供这些组件的方法。

公开(公告)号：US09159638B2

公开(公告)日：2015-10-13

申请号：US13116201

申请日：2011-05-26

Applicant: Kuo-Chin Chang ,  Yuh Chern Shieh

Inventor： Kuo-Chin Chang ,  Yuh Chern Shieh

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76837 ,  H01L23/3171 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01327 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.

Abstract translation: 本发明涉及半导体器件的凸块结构。 半导体器件的示例性结构包括衬底; 衬底上的接触垫; 钝化层，其延伸在所述衬底上并且具有在所述接触焊盘上的第一宽度的开口; 开口内的导电通孔; 以及具有完全覆盖所述导电通孔的第二宽度的导电柱，其中所述第一宽度与所述第二宽度的比率为约0.15至0.55。

公开(公告)号：US20120286417A1

公开(公告)日：2012-11-15

申请号：US13105360

申请日：2011-05-11

Applicant: Tsung-Shu Lin ,  Yuh Chern Shieh ,  Kuo-Chin Chang

Inventor： Tsung-Shu Lin ,  Yuh Chern Shieh ,  Kuo-Chin Chang

IPC: H01L23/485 ,  G06F17/50 ,  H01L21/58

CPC classification number: H01L23/562 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15321 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.

Abstract translation: 一种方法包括确定集成电路（IC）封装设计的翘曲。 IC封装设计包括在第一主表面上具有顶部焊接掩模的基板和与第一主表面相对的第二主表面上的底部焊接掩模。 第一主表面上安装有IC芯片，顶部焊接掩模。 该设计被修改，包括修改由顶部焊接掩模和底部焊接掩模组成的组中的一个的平均厚度，以便减少翘曲。 根据改进的设计制造IC封装。

公开(公告)号：US20080174002A1

公开(公告)日：2008-07-24

申请号：US11655844

申请日：2007-01-22

Applicant: Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

Inventor： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

IPC: H01L23/488 ,  H01L21/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

Abstract translation: 提供一种制造半导体封装的方法。 在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。 提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。 半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并与暴露的通孔塞的表面接触。 然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。 在多个通孔塞的相对端的表面上形成多个UBM层。 多个焊料凸起形成并安装在UBM层上。 提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。 多个焊球形成并安装在第二基板的第二表面上。 第三衬底安装到焊球。

公开(公告)号：US20070246821A1

公开(公告)日：2007-10-25

申请号：US11408155

申请日：2006-04-20

Applicant: Szu Lu ,  Clinton Chao ,  Tjandra Karta ,  Jerry Tzou ,  Kuo-Chin Chang

Inventor： Szu Lu ,  Clinton Chao ,  Tjandra Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L21/563 ,  H01L21/6835 ,  H01L23/055 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the package substrate from a second surface opposite the first surface wherein the semiconductor material is substantially removed, and attaching ball grid array (BGA) balls to deep vias exposed on the second surface of the package substrate after thinning the package substrate.

Abstract translation: 提供了具有减小的应力的半导体封装组件及其形成方法。 该方法包括提供包括基材的封装衬底，形成覆盖封装衬底的互连结构，将至少一个芯片附接到封装衬底的第一表面，使封装衬底从与第一表面相反的第二表面变薄，其中半导体 基本上去除了材料，并且在将封装衬底细化之后，将球栅阵列（BGA）球附着到在封装衬底的第二表面上暴露的深通孔。