公开(公告)号：US09093411B2

公开(公告)日：2015-07-28

申请号：US12984669

申请日：2011-01-05

Applicant: Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/34 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5383 ,  H01L24/05 ,  H01L29/0649 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/00

Abstract: A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.

Abstract translation: 描述用于晶片测试的半导体晶片中的焊盘结构。 焊盘结构包括至少两个连接在其上的金属焊盘，其间通过一个或多个绝缘层中的多个导电签证。 与最底部的金属焊盘接触的多个接触棒从最底部的金属焊盘基本垂直地延伸到衬底中。 隔离结构基本上围绕多个接触杆以隔离垫结构。

公开(公告)号：US09021682B2

公开(公告)日：2015-05-05

申请号：US13527459

申请日：2012-06-19

Applicant: Chien Ling Hwang ,  Yeong-Jyh Lin ,  Yi-Li Hsiao ,  Ming-Da Cheng ,  Tsai-Tsung Tsai ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Yi-Li Hsiao ,  Ming-Da Cheng ,  Tsai-Tsung Tsai ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01R43/052 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L24/13 ,  H01L24/78 ,  H01L2224/056 ,  H01L2224/1111 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48 ,  H01L2224/7855 ,  H01L2224/78621 ,  H01L2224/85051 ,  H01L2224/854 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/206 ,  Y10T29/49192 ,  Y10T29/49213 ,  Y10T29/514 ,  Y10T29/5177 ,  Y10T29/53217 ,  Y10T29/53235 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01049 ,  H01L2224/4554

Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.

Abstract translation: 一种装置包括：线圈，其被配置为供应线，被配置为在所述线中形成切口的切割装置，以及被配置为结合所述线并形成柱形凸块的毛细管。 该设备还被配置为拉动线在凹口处断裂，尾部区域附接到柱形凸块。

公开(公告)号：US08749043B2

公开(公告)日：2014-06-10

申请号：US13409756

申请日：2012-03-01

Applicant: Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC: H01L23/02 ,  H01L21/16

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

Abstract translation: 包装结构包括第一包装和第二包装通过引入连接到第二包装件上的导热基材提供改进的热传导和机械强度。 第一封装具有第一衬底和第一集成电路。 第二包装具有包含通孔的第二基板，其具有第一热膨胀系数。 第二封装还具有第二集成电路，其具有位于第二基板上的第二热膨胀系数。 第二热膨胀系数从第一热膨胀系数偏离每摄氏度小于约10或小于约5百万分之一。 第一组导电元件将第一基板和第二基板连接。 第二组导电元件将第二基板和第二集成电路耦合。

公开(公告)号：US08735273B2

公开(公告)日：2014-05-27

申请号：US13179299

申请日：2011-07-08

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract translation: 一种方法包括在覆盖半导体衬底的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。

公开(公告)号：US20140021605A1

公开(公告)日：2014-01-23

申请号：US13552375

申请日：2012-07-18

Applicant: Chen-Hua Yu ,  Yung Ching Chen ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Mirng-Ji Lii ,  Ming-Da Cheng

Inventor： Chen-Hua Yu ,  Yung Ching Chen ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Mirng-Ji Lii ,  Ming-Da Cheng

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/68778 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.

Abstract translation: 封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP器件包括第一封装管芯和耦合到第一封装管芯的第二封装管芯。 在第一封装模具和第二封装模具之间设置金属凸块凸块。 金属柱凸块包括一个棒状区域，一个耦合到该棒状区域的第一端的第一球形区域和一个耦合到该棒状区域的第二端的第二球形区域。 金属柱凸块包括部分嵌入焊点中的部分。

公开(公告)号：US20140004660A1

公开(公告)日：2014-01-02

申请号：US13539188

申请日：2012-06-29

Applicant: Ming-Chung Sung ,  Yung Ching Chen ,  Chien-Hsiun Lee ,  Chen-Hua Yu ,  Mirng-Ji Lii

Inventor： Ming-Chung Sung ,  Yung Ching Chen ,  Chien-Hsiun Lee ,  Chen-Hua Yu ,  Mirng-Ji Lii

IPC: H01L21/50

CPC classification number: H01L21/4825 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/742 ,  H01L24/78 ,  H01L2224/1134 ,  H01L2224/45144 ,  H01L2224/742 ,  H01L2224/78 ,  H01L2224/78301 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.

Abstract translation: 本文公开了一种用于通过形成一个或多个互连件，可选地用引线键合器安装半导体封装以及将互连件安装到目标封装上的安装焊盘来安装半导体封装件的系统和方法。 安装互连可以包括将互连件超声波焊接到安装焊盘，并且互连可以经由互连端部上的安装节点来安装，其中安装节点可以由电火焰熄灭工艺形成。 互连可以被修剪到一个或多个基本均匀的高度，可选地使用激光或接触式修剪系统，并且在修剪期间可以支撑互连的尾部。 顶部封装可以结合在互连件的修剪端上。 在安装期间，可以使用支撑板来支撑封装，并且在互连安装期间可以使用掩模。

公开(公告)号：US08540136B1

公开(公告)日：2013-09-24

申请号：US13605403

申请日：2012-09-06

Applicant: Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: B23K31/02 ,  B23K37/00

CPC classification number: B23K31/02 ,  B21D53/36 ,  B23K20/007 ,  H01L2224/78301 ,  Y10T29/49

Abstract: Methods for forming stud bumps and apparatuses for forming stud bumps are disclosed. According to an embodiment, a method includes clamping a wire with a clamp. The clamp includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method further includes bonding the wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface. The second notch is the notch pitch distance from the first notch along the wire.

Abstract translation: 公开了用于形成柱形凸块的方法和用于形成凸块凸块的装置。 根据实施例，一种方法包括用夹具夹紧线。 所述夹具包括至少两个相对的板，并且当所述线被夹紧形成所述线中的第一凹口时，所述相对板中的至少一个包括与所述线相交的突出特征。 该方法还包括将线接合到接合表面，将线从夹具中释放出来，使线穿过钳口的间距距离通过夹具夹紧线，夹具在线中形成第二凹口，并将线断开， 接合表面上的导线的接合部分。 第二个凹口是距离第一个凹口沿导线的切口间距距离。

公开(公告)号：US20130228932A1

公开(公告)日：2013-09-05

申请号：US13409756

申请日：2012-03-01

Applicant: Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

公开(公告)号：US08524595B2

公开(公告)日：2013-09-03

申请号：US12614727

申请日：2009-11-09

Applicant: Mirng-Ji Lii ,  Hsin-Hui Lee

Inventor： Mirng-Ji Lii ,  Hsin-Hui Lee

IPC: H01L21/60

CPC classification number: H01L23/3192 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/274 ,  H01L2224/81191 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/013

Abstract: A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.

Abstract translation: 半导体结构包括在第一基板和第二基板之间的多个焊料结构。 第一封装材料基本上围绕第一种焊料结构，第二封装材料基本上围绕第二种焊料结构。 第一个和第二个焊料结构彼此靠近，第一封装材料和第二封装材料之间有一个间隙。

公开(公告)号：US20130009307A1

公开(公告)日：2013-01-10

申请号：US13179299

申请日：2011-07-08

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract translation: 一种方法包括在覆盖在半导体衬底上的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。