公开(公告)号：US07271480B2

公开(公告)日：2007-09-18

申请号：US11237924

申请日：2005-09-29

Applicant: Kuo-Chin Chang ,  Ching-Yu Ni

Inventor： Kuo-Chin Chang ,  Ching-Yu Ni

IPC: H01L23/20

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/562 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/15311

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract translation: 提供了用于加强集成电路封装的约束加强件。 在一个实施例中，约束加强件包括用于结合到集成电路基板的刚性平面基座元件。 基座元件具有多个细长的支撑构件，并且基座元件具有用于围绕集成电路的开口。 基部元件和支撑构件由于至少集成电路和基板之间的热膨胀失配而减少翘曲。 在一个实施例中，细长支撑构件可从基座元件的角部拆卸。 在另一个实施例中，细长支撑构件具有用于附接和分离到基部元件的角部的装置。 在另一个实施例中，细长的支撑构件可从基部元件的中央部分的周围拆卸。 在另一个实施例中，细长的支撑构件具有用于附接和分离到基部元件的中部的装置。

公开(公告)号：US20070069366A1

公开(公告)日：2007-03-29

申请号：US11237924

申请日：2005-09-29

Applicant: Kuo-Chin Chang ,  Ching-Yu Ni

Inventor： Kuo-Chin Chang ,  Ching-Yu Ni

IPC: H01L23/12

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/562 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/15311

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract translation: 提供了用于加强集成电路封装的约束加强件。 在一个实施例中，约束加强件包括用于结合到集成电路基板的刚性平面基座元件。 基座元件具有多个细长的支撑构件，并且基座元件具有用于围绕集成电路的开口。 基部元件和支撑构件由于至少集成电路和基板之间的热膨胀失配而减少翘曲。 在一个实施例中，细长支撑构件可从基座元件的角部拆卸。 在另一个实施例中，细长支撑构件具有用于附接和分离到基部元件的角部的装置。 在另一个实施例中，细长的支撑构件可从基部元件的中央部分的周围拆卸。 在另一个实施例中，细长的支撑构件具有用于附接和分离到基部元件的中部的装置。

公开(公告)号：US08410599B2

公开(公告)日：2013-04-02

申请号：US12756915

申请日：2010-04-08

Applicant: Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC: H01L23/04

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US07968448B2

公开(公告)日：2011-06-28

申请号：US12466656

申请日：2009-05-15

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract translation: 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US08541877B2

公开(公告)日：2013-09-24

申请号：US12849089

申请日：2010-08-03

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC: H01L23/48

CPC classification number: H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US20100289092A1

公开(公告)日：2010-11-18

申请号：US12756915

申请日：2010-04-08

Applicant: Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

Inventor： Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC: H01L29/78 ,  H01L23/538

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US08564123B2

公开(公告)日：2013-10-22

申请号：US13011184

申请日：2011-01-21

Applicant: Ching-Yu Ni ,  Chang-Sheng Hsu

Inventor： Ching-Yu Ni ,  Chang-Sheng Hsu

IPC: H01L23/10

CPC classification number: H01L21/78 ,  B81B7/0051 ,  B81C2203/0118 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/585 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2732 ,  H01L2224/27618 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包含具有芯片的半导体衬底。 封装层设置在半导体衬底上。 间隔件设置在半导体衬底和封装层之间，其中由半导体衬底，间隔件和封装层组成的侧表面具有凹部。 该方法包括在半导体晶片的多个芯片和封装层之间形成多个间隔物，其中对应于每个芯片的每个间隔件彼此分离，并且间隔件从芯片的边缘向内收缩以形成凹部 并且沿着任何两个相邻芯片之间的划线切割半导体晶片以形成多个芯片封装。

公开(公告)号：US08431950B2

公开(公告)日：2013-04-30

申请号：US12471255

申请日：2009-05-22

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract translation: 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。

公开(公告)号：US20110140248A1

公开(公告)日：2011-06-16

申请号：US13030887

申请日：2011-02-18

Applicant: Chia-Lun TSAI ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

Inventor： Chia-Lun TSAI ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC: H01L23/552 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract translation: 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US20110042783A1

公开(公告)日：2011-02-24

申请号：US12843869

申请日：2010-07-26

Applicant: Ching-Yu Ni

Inventor： Ching-Yu Ni

IPC: H01L29/92 ,  H01L21/02 ,  H01L29/86

CPC classification number: H01L28/60 ,  H01F17/0013 ,  H01F41/041 ,  H01L27/12 ,  H01L28/10

Abstract: An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate, a patterned semiconductor substrate, having at least one opening, disposed on the glass substrate and at least one passive component having a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate.

Abstract translation: 提供了一种电子设备及其制造方法。 该电子装置包括玻璃基板，具有至少一个开口的图案化半导体基板，设置在玻璃基板上，以及至少一个无源部件，具有第一导电层和第二导电层，其中第一导电层设置在 图案化的半导体衬底和玻璃衬底。