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    Surface treatment of metal interconnect lines
    2.
    发明授权
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US08053894B2

    公开(公告)日：2011-11-08

    申请号：US11213238

    申请日：2005-08-26

    申请人： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    发明人： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    摘要翻译： 用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

    Zirconium oxide and hafnium oxide etching using halogen containing chemicals
    3.
    发明授权
    Zirconium oxide and hafnium oxide etching using halogen containing chemicals 有权
    使用含卤素化学品的氧化锆和氧化铪蚀刻

    公开(公告)号：US07012027B2

    公开(公告)日：2006-03-14

    申请号：US10766596

    申请日：2004-01-27

    申请人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

    发明人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

    IPC分类号： H01L21/31

    CPC分类号： H01L21/3065 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66583

    摘要： A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

    摘要翻译： 描述了一种相对于氧化硅，多晶硅或硅选择性地蚀刻优选为铪或氧化锆，硅酸盐，氮化物或氮氧化物的高k电介质层的方法，其选择性大于2:1。 等离子体蚀刻化学性质由一种或多种含卤素气体组成，例如CF 4，CH 3 3，CH 2 F 2， CH 3，CH 3，CH 3，CH 3，CH 3，CH 3，CH 3， C 5，C 5，F 5，BCl 3，Br 2，HF，HCl，HBr，HI， 和NF 3，并且不留下蚀刻残留物。 可以向含卤素的气体中加入惰性气体或惰性气体和氧化剂气体。 在一个实施例中，在MOS晶体管的有源区域的部分上去除高k栅极电介质层。 或者，高k电介质层用于两个导电层之间的电容器中，并且从ILD层的部分选择性地去除。

    Process for patterning high-k dielectric material
    4.
    发明申请
    Process for patterning high-k dielectric material 有权
    图案化高k电介质材料的工艺

    公开(公告)号：US20050181590A1

    公开(公告)日：2005-08-18

    申请号：US11101774

    申请日：2005-04-08

    申请人： Hsien-Kuang Chiu ,  Baw-Ching Perng ,  Hun-Jan Tao

    发明人： Hsien-Kuang Chiu ,  Baw-Ching Perng ,  Hun-Jan Tao

    IPC分类号： C23F1/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/78

    CPC分类号： H01L21/31144 ,  H01L21/31116

    摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

    摘要翻译： 提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。 在高k电介质层上进行第一蚀刻。 在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。 执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。 第二蚀刻不同于第一蚀刻。 优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。 该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

    Integrated approach for controlling top dielectric loss during spacer etching
    5.
    发明授权
    Integrated approach for controlling top dielectric loss during spacer etching 有权
    在间隔蚀刻期间控制顶部介电损耗的集成方法

    公开(公告)号：US06498067B1

    公开(公告)日：2002-12-24

    申请号：US10139021

    申请日：2002-05-02

    申请人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

    发明人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

    IPC分类号： H01L21336

    CPC分类号： H01L29/665 ,  H01L29/6656

    摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.

    摘要翻译： 已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。 该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。 重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物 间隔

    CMOS devices with improved gap-filling
    8.
    发明申请
    CMOS devices with improved gap-filling 有权
    具有改进间隙填充的CMOS器件

    公开(公告)号：US20070235823A1

    公开(公告)日：2007-10-11

    申请号：US11393369

    申请日：2006-03-30

    申请人： Ju-Wang Hsu ,  Chih-Hsin Ko ,  Jyu-Horng Shieh ,  Baw-Ching Perng ,  Syun-Ming Jang

    发明人： Ju-Wang Hsu ,  Chih-Hsin Ko ,  Jyu-Horng Shieh ,  Baw-Ching Perng ,  Syun-Ming Jang

    IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843 ,  Y10S438/981

    摘要： A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.

    摘要翻译： 半导体结构包括衬底和在衬底的第一区域上的第一MOS器件，其中第一MOS器件包括第一间隔衬垫。 半导体结构还包括在第二区域上的第二MOS器件，其中第二MOS器件包括第二间隔衬垫。 在第一MOS器件上形成具有第一厚度的第一应力膜，并直接在第一间隔衬垫上。 在第二MOS器件上形成具有第二厚度的第二应力膜，并且直接在第二间隔衬垫上。 第一和第二应力膜可以由相同的材料形成。

    Process for removing organic materials during formation of a metal interconnect
    10.
    发明授权
    Process for removing organic materials during formation of a metal interconnect 有权
    在形成金属互连件期间去除有机材料的方法

    公开(公告)号：US07122484B2

    公开(公告)日：2006-10-17

    申请号：US10833558

    申请日：2004-04-28

    申请人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

    发明人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

    IPC分类号： H01L21/469 ,  H01L21/44

    CPC分类号： H01L21/76814 ,  C11D3/3947 ,  C11D7/50 ,  C11D11/0047 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76808

    摘要： A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

    摘要翻译： 公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。 将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。 可以加入螯合剂以保护金属层免于氧化。 可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。 可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。 去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。