公开(公告)号：US11837645B2

公开(公告)日：2023-12-05

申请号：US18085871

申请日：2022-12-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yoontae Hwang ,  Wandon Kim ,  Geunwoo Kim ,  Heonbok Lee ,  Taegon Kim ,  Hanki Lee

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L21/285

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76886 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

摘要： A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US20230387240A1

公开(公告)日：2023-11-30

申请号：US18447183

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L21/306 ,  H01L21/764 ,  H01L21/02

CPC分类号： H01L29/45 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/764 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66553 ,  H01L29/66742

摘要： Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

公开(公告)号：US20230377989A1

公开(公告)日：2023-11-23

申请号：US18365832

申请日：2023-08-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC分类号： H01L21/8238 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L21/823814 ,  H01L29/45 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/0332 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/78618

摘要： A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US20230369102A1

公开(公告)日：2023-11-16

申请号：US18358707

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ta YU ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Yen-Chieh HUANG ,  Feng-Cheng YANG

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/532 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535

CPC分类号： H01L21/7682 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/45 ,  H01L23/5329 ,  H01L29/66795 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535

摘要： A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

公开(公告)号：US20230369055A1

公开(公告)日：2023-11-16

申请号：US18359735

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L21/76814 ,  H01L21/02063 ,  H01L21/76895 ,  H01L21/31155 ,  H01L21/31111 ,  H01L21/76805

摘要： The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US20230363205A1

公开(公告)日：2023-11-09

申请号：US18351612

申请日：2023-07-13

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION ,  SONY GROUP CORPORATION

发明人： TAKASHI YAMAZAKI ,  KAZUHIRO TAMURA

IPC分类号： H10K59/121 ,  G09G3/3233 ,  H01L21/285 ,  H01L29/45 ,  H10K71/00

CPC分类号： H10K59/1213 ,  G09G3/3233 ,  H01L21/28518 ,  H01L29/456 ,  H10K71/00 ,  G09G2320/0233 ,  G09G2320/0238 ,  H10K59/1201

摘要： [Abstract] [Object] To provide a display device in which the occurrence of a bright spot defect is suppressed. [Solving Means] The display device includes a light-emitting portion and a drive circuit. The drive circuit includes a transistor that drives the light-emitting portion and includes a first diffusion layer and a first contact electrode, the first diffusion layer including no silicide formed in a silicon region, the first contact electrode being electrically connected to the first diffusion layer.

公开(公告)号：US20230354600A1

公开(公告)日：2023-11-02

申请号：US18346056

申请日：2023-06-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han LIN ,  Wei Cheng WU

IPC分类号： H10B41/47 ,  H01L29/423 ,  H01L21/285 ,  H01L29/788 ,  H01L21/306 ,  H01L29/66 ,  H10B41/30 ,  H10B99/00

CPC分类号： H10B41/47 ,  H01L29/42328 ,  H01L21/28518 ,  H01L29/788 ,  H01L21/30625 ,  H01L29/66825 ,  H10B41/30 ,  H10B99/00

摘要： A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US11804533B2

公开(公告)日：2023-10-31

申请号：US18173541

申请日：2023-02-23

申请人： Acorn Semi, LLC

发明人： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC分类号： H01L29/47 ,  H01L21/285 ,  H01L29/04 ,  H01L21/283 ,  H01L29/45 ,  H01L21/324 ,  H01L29/161

CPC分类号： H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

摘要： Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

公开(公告)号：US11804516B2

公开(公告)日：2023-10-31

申请号：US17118078

申请日：2020-12-10

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-yeol Kim ,  Hyon-wook Ra ,  Seo-bum Lee ,  Jun-soo Kim ,  Chung-hwan Shin

IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L29/78 ,  H01L29/51 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01L28/20 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/5283 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/785 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53223 ,  H01L29/517 ,  H01L29/7846

摘要： A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

公开(公告)号：US11799015B2

公开(公告)日：2023-10-24

申请号：US17703884

申请日：2022-03-24

申请人： Intel Corporation

发明人： Tahir Ghani ,  Byron Ho ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H10B10/00 ,  H01L23/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.