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    RELATING TO SOI WAFERS AND DEVICES WITH BURIED STRESSORS
    4.
    发明申请
    RELATING TO SOI WAFERS AND DEVICES WITH BURIED STRESSORS 有权

    公开(公告)号：US20220223735A1

    公开(公告)日：2022-07-14

    申请号：US17657854

    申请日：2022-04-04

    申请人： Acorn Semi, LLC

    发明人： Paul A. Clifton ,  Andreas Goebel

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10

    摘要： A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

    MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR
    5.
    发明申请
    MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR 审中-公开

    公开(公告)号：US20200152758A1

    公开(公告)日：2020-05-14

    申请号：US16742098

    申请日：2020-01-14

    申请人： Acorn Semi, LLC

    发明人： Paul A. Clifton ,  Andreas Goebel

    IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/36

    摘要： An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    MIS contact structure with metal oxide conductor
    6.
    发明授权
    MIS contact structure with metal oxide conductor 有权

    公开(公告)号：US11843040B2

    公开(公告)日：2023-12-12

    申请号：US17094651

    申请日：2020-11-10

    申请人： Acorn Semi, LLC

    发明人： Paul A. Clifton ,  Andreas Goebel

    IPC分类号： H01L29/49 ,  H01L29/08 ,  H01L29/36 ,  H01L29/51 ,  H01L29/66 ,  H04L67/10 ,  H04L67/51 ,  H01L21/28

    CPC分类号： H01L29/4966 ,  H01L21/28017 ,  H01L29/0895 ,  H01L29/36 ,  H01L29/517 ,  H01L29/66643 ,  H04L67/10 ,  H04L67/51

    摘要： An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
    8.
    发明授权
    Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers 有权

    公开(公告)号：US11610974B2

    公开(公告)日：2023-03-21

    申请号：US17247803

    申请日：2020-12-23

    申请人： Acorn Semi, LLC

    发明人： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

    IPC分类号： H01L29/47 ,  H01L21/285 ,  H01L29/04 ,  H01L21/283 ,  H01L29/45 ,  H01L21/324 ,  H01L29/161

    摘要： Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.