公开(公告)号：US06646347B2

公开(公告)日：2003-11-11

申请号：US09998507

申请日：2001-11-30

Applicant: Lei L. Mercado ,  Vijay Sarihan ,  Young Sir Chung ,  James Jen-Ho Wang ,  Edward R. Prack

Inventor： Lei L. Mercado ,  Vijay Sarihan ,  Young Sir Chung ,  James Jen-Ho Wang ,  Edward R. Prack

IPC: H01L2348

CPC classification number: H01L24/12 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05599 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05644 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0567 ,  H01L2224/05671 ,  H01L2224/05679 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

Abstract: In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).

公开(公告)号：US20240290735A1

公开(公告)日：2024-08-29

申请号：US18174693

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： RAFAEL JOSE GUEVARA ,  JESSAMAE GRATE

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03502 ,  H01L2224/03831 ,  H01L2224/03848 ,  H01L2224/03912 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/05618 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11831 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/0132

Abstract: A method includes forming a seed layer on a substrate. The seed layer includes a first metal. The method also includes forming a first metal layer over the seed layer. The first metal layer includes a second metal. The method further includes forming a second metal layer over the first metal layer. The second metal layer includes the first metal. The method includes converting at least a portion of the first metal layer into an alloy of the first metal and the second metal. The seed layer is then etched.

公开(公告)号：US11664335B2

公开(公告)日：2023-05-30

申请号：US15358038

申请日：2016-11-21

Applicant: Semikron Elektronik GmbH & Co., KG

Inventor： Wolfgang-Michael Schulz

IPC: H01L23/00 ,  H01L23/488

CPC classification number: H01L24/05 ,  H01L23/488 ,  H01L24/03 ,  H01L24/08 ,  H01L24/48 ,  H01L24/85 ,  H01L24/45 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03462 ,  H01L2224/03823 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/0508 ,  H01L2224/0516 ,  H01L2224/05023 ,  H01L2224/0558 ,  H01L2224/0566 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05583 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/05684 ,  H01L2224/08503 ,  H01L2224/45005 ,  H01L2224/45015 ,  H01L2224/4554 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48247 ,  H01L2224/48506 ,  H01L2224/48507 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/2076 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05179 ,  H01L2924/00014 ,  H01L2224/05172 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/0516 ,  H01L2924/00014 ,  H01L2224/05118 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/01074 ,  H01L2224/05186 ,  H01L2924/01022 ,  H01L2224/45005 ,  H01L2924/2076 ,  H01L2224/45147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/43848 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/01014

Abstract: A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

公开(公告)号：US20230154885A1

公开(公告)日：2023-05-18

申请号：US18049428

申请日：2022-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Jiyeong Kim ,  Okseon Yoon

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L24/73 ,  H01L21/563 ,  H01L23/295 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/1317 ,  H01L2224/1318 ,  H01L2224/2929 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05617 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/16146 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.

公开(公告)号：US20180200840A1

公开(公告)日：2018-07-19

申请号：US15746536

申请日：2016-07-19

Applicant: Northeastem University ,  University of North Florida

Inventor： Stephen Peter Stagon ,  Hanchen Huang ,  Paul Robert Elliott

IPC: B23K35/26 ,  B23K35/02 ,  H01L23/00

CPC classification number: B23K35/264 ,  B23K35/02 ,  B23K35/0227 ,  B23K35/0261 ,  B23K35/26 ,  B23K2101/40 ,  B23K2101/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05583 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/27418 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/2782 ,  H01L2224/29005 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29205 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/3201 ,  H01L2224/32012 ,  H01L2224/32501 ,  H01L2224/32506 ,  H01L2224/83099 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2924/01014 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/0102

Abstract: Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

公开(公告)号：US09520381B2

公开(公告)日：2016-12-13

申请号：US14592576

申请日：2015-01-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yuichi Higuchi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05617 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06593 ,  H01L2924/01032 ,  H01L2924/207 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/381 ,  H01L2924/384 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01029

Abstract: A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

Abstract translation: 半导体器件包括其中第一半导体芯片和第二半导体芯片结合在一起的多层芯片。 第一电极焊盘形成在第一半导体芯片的主表面上，并且在第一电极焊盘上形成第一突起。 在第二半导体芯片的主表面上形成第二凸起，使得第二凸块与第一凸块接合。 第一电极焊盘具有开口，并且开口和形成台阶状的开口的整个周边部分形成阶梯形状。 第一凸块具有在其中心凹陷并且覆盖阶梯形状的凹陷形状。

公开(公告)号：US20160071824A1

公开(公告)日：2016-03-10

申请号：US14725268

申请日：2015-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongwon Yoon ,  Boin Noh ,  Baikwoo Lee ,  Hyunsuk Chun

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11436 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05618

Abstract: Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.

Abstract translation: 提供一种半导体封装及其制造方法，包括第一封装衬底; 安装在第一封装基板上并具有第一焊盘和第二焊盘的第一半导体芯片，其中第一焊盘设置在第一半导体芯片的顶部上，第二焊盘设置在第一半导体芯片的底部， 底部是顶部的相对表面; 以及设置在所述第一焊盘上并且将所述第一半导体芯片电连接到设置在所述第一半导体芯片的顶部上的第二半导体芯片和第二封装基板中的一个的复合金属。

公开(公告)号：US20160043054A1

公开(公告)日：2016-02-11

申请号：US14451868

申请日：2014-08-05

Applicant: Infineon Technologies AG

Inventor： Rupert Fischer ,  Peter Strobel ,  Joachim Mahler ,  Konrad Roesl ,  Alexander Heinrich

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49575 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/04026 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8381 ,  H01L2224/8382 ,  H01L2224/83851 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95091 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00

Abstract: Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

Abstract translation: 公开了将芯片连接到芯片载体的方法。 在一些实施例中，用于将多个芯片连接到芯片载体的方法包括将第一芯片放置在转移载体上，将第二芯片放置在转移载体上，将具有第一和第二芯片的转移载体放置在芯片载体上并形成 第一芯片和芯片载体以及第二芯片和芯片载体。

公开(公告)号：US09000575B2

公开(公告)日：2015-04-07

申请号：US13403338

申请日：2012-02-23

Applicant: Hideo Imai

Inventor： Hideo Imai

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/562 ,  H01L25/0657 ,  H01L25/074 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/00

Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.

公开(公告)号：US20150028473A1

公开(公告)日：2015-01-29

申请号：US14245618

申请日：2014-04-04

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 提供堆栈包。 堆叠包装包括第一芯片和第二芯片。 第一芯片包括第一芯片体，穿过第一芯片体的第一穿透电极和设置在第一芯片主体的底表面上的绝缘层。 第二芯片包括设置在第二芯片主体的顶表面上的第二芯片体和凸块。 第一和第二芯片垂直堆叠，使得凸块穿透绝缘层以刺穿第一通孔，第二芯片体的顶表面直接接触绝缘层。 还提供了相关的制造方法，电子系统和存储卡。