公开(公告)号：US20170069587A1

公开(公告)日：2017-03-09

申请号：US15356316

申请日：2016-11-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

摘要： A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

摘要翻译： 凸块结构包括形成在衬底上的接触元件和覆盖衬底的钝化层。 钝化层包括暴露接触元件的钝化开口。 凸起结构还包括覆盖钝化层的聚酰亚胺层和电耦合到接触元件的凸块下金属（UBM）特征。 聚酰亚胺层具有暴露接触元件的聚酰亚胺开口，凸起下的金属特征具有UBM宽度。 凸起结构还包括在凸起下金属冶金特征上的铜柱。 铜柱的前端具有柱宽，UBM宽度大于柱宽。

公开(公告)号：US09564345B1

公开(公告)日：2017-02-07

申请号：US14828946

申请日：2015-08-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Tien-Chung Yang ,  Lin-Chih Huang ,  Hsien-Wei Chen ,  An-Jhih Su ,  Li-Hsien Huang

IPC分类号： H01L29/06 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L23/3114 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11466 ,  H01L2224/11602 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/03

摘要： A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.

摘要翻译： 半导体器件包括半导体衬底，半导体衬底上的导电焊盘和导电焊盘上的导体。 半导体器件还具有设置在半导体衬底上并围绕导体的聚合材料。 半导体器件还包括在导体和聚合物材料之间的导电层。 在半导体器件中，导电层和聚合物材料之间的粘合强度大于聚合材料和导体之间的粘附强度。

公开(公告)号：US20170005053A1

公开(公告)日：2017-01-05

申请号：US15255588

申请日：2016-09-02

申请人： International Business Machines Corporation

发明人： Akihiro HORIBE ,  Keiji MATSUMOTO ,  Keishi OKAMOTO ,  Kazushige TORIYAMA

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  B23K3/0623 ,  H01L21/4867 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/34 ,  H01L23/345 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/11013 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/11416 ,  H01L2224/1148 ,  H01L2224/11618 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17519 ,  H01L2224/27 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29076 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00012

摘要： Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

摘要翻译： 通过使用具有能够减小施加在倒装芯片连接的芯片上的应力的形状的基板来实现高度可靠的芯片安装，使得施加在芯片上的应力减小，并且具有低的层间绝缘层的分离 介电常数（low-k）最小。 具体地，在芯片安装结构中，示出了具有低介电常数（低-k）的层间绝缘层的芯片通过凸块倒装芯片连接到基板。 在芯片安装结构中，基板具有这样的形状，使得由于热应力而在芯片的角部施加在层间绝缘层上的机械应力减小，由于热膨胀系数之间的差异导致的热应力 芯片和基板。

公开(公告)号：US09472522B2

公开(公告)日：2016-10-18

申请号：US14074333

申请日：2013-11-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/09 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0214 ,  H01L2224/02175 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/0912 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/00012

摘要： Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

摘要翻译： 公开了用于半导体器件的封装装置及其制造方法。 在一些实施例中，包装装置包括设置在衬底上的接触垫，以及设置在衬底上的钝化层和接触垫的第一部分，接触垫的第二部分被暴露。 后钝化互连（PPI）线设置在钝化层上并且耦合到接触焊盘的第二部分。 PPI垫设置在钝化层上方并耦合到PPI线。 绝缘材料设置在PPI线上，PPI垫被暴露。 绝缘材料与PPI垫的边缘部分隔开预定距离。

公开(公告)号：US09401339B2

公开(公告)日：2016-07-26

申请号：US14277343

申请日：2014-05-14

申请人： Weng F. Yap ,  Alan J. Magnus

发明人： Weng F. Yap ,  Alan J. Magnus

IPC分类号： H01L23/52 ,  H01L23/00 ,  B23K1/20 ,  B23K1/00 ,  H01L23/31 ,  B23K3/06

CPC分类号： H01L24/20 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/02166 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13016 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/0132

摘要： Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

摘要翻译： 提供了晶圆级封装以及用于生产具有不可润湿的焊锡圈的晶片级封装的方法。 在一个实施例中，该方法包括在暴露焊料掩模层下面的图案化金属层的区域的焊料掩模层中形成焊接掩模开口。 在焊料掩模层中形成焊接掩模开口之前或之后，产生部分地在图案化金属层的暴露区域上延伸的不可润湿的焊接套环。 将焊球沉积在不可润湿的焊接环上并进入焊接掩模开口中，使得周边间隙设置在限定焊料掩模开口的焊料球的基部和焊料掩模层的侧壁周围。

公开(公告)号：US20160056116A1

公开(公告)日：2016-02-25

申请号：US14930984

申请日：2015-11-03

申请人： International Business Machines Corporation

发明人： Toyohiro Aoki ,  Hiroyuki Mori ,  Kazushige Toriyama

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  B23K3/0623 ,  H01L21/4867 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/34 ,  H01L23/345 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/11013 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/11416 ,  H01L2224/1148 ,  H01L2224/11618 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17519 ,  H01L2224/27 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29076 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00012

摘要： A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

摘要翻译： 基板接合方法能够可靠地接合基板，同时避免产率的降低，由较细的间距变差。 基板接合方法可以包括：在已经形成有焊盘的第一基板的表面上形成粘合树脂层; 在所述垫上方的所述粘合树脂层上形成开口; 用熔融焊料填充开口以形成柱状焊料凸块; 以及在形成在所述第二基板上的端子与所述焊料凸块对准的同时向所述第一基板和第二基板施加热和压力。

公开(公告)号：US09111817B2

公开(公告)日：2015-08-18

申请号：US13712722

申请日：2012-12-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guan-Yu Chen ,  Yu-Wei Lin ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

摘要： An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

摘要翻译： 轨迹（BOT）结构上的实施例凸块包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下金属（UBM）特征，凸起下金属冶金特征上的金属凸块，以及衬底迹线 衬底，通过焊接接头和金属间化合物耦合到金属凸块的衬底迹线，金属间化合物的第一横截面积与焊料接头的第二横截面积的比率大于百分之四十。

公开(公告)号：US20150214186A1

公开(公告)日：2015-07-30

申请号：US14165280

申请日：2014-01-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Chao Mao ,  Jing-Cheng Lin

IPC分类号： H01L23/00 ,  H01L21/311 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/11013 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.

摘要翻译： 一种封装半导体器件的方法，包括：将多个管芯附接到载体晶片，其中每个所述管芯包括顶表面; 在所述模具上形成模塑料层，其中所述模具的顶表面被所述模塑复合层覆盖; 去除模制化合物层的第一部分; 去除模制化合物层的第二部分，使得模具的顶表面不被模塑料层覆盖; 在模具的顶表面上形成再分布层（RDL）; 在所述RDL的至少一部分上形成多个焊球; 并分割模具。

公开(公告)号：US20150118796A1

公开(公告)日：2015-04-30

申请号：US14583984

申请日：2014-12-29

申请人： Micron Technology, Inc.

发明人： Young Do Kweon ,  Tongbi Jiang

IPC分类号： H01L23/00 ,  H01L21/78

CPC分类号： H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/05599

摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

摘要翻译： 本文公开了在半导体工件上形成多个微电子器件的微电子器件和方法。 一种这样的方法包括将多个第一互连元件放置在半导体工件的一侧上，在工件侧面上形成层，通过加热第一互连元件来重塑第一互连元件，以及将多个第一互连元件的第一部分 单独的第二互连元件到相应的第一互连元件，其中所述单个第二互连元件的第二部分被暴露。

公开(公告)号：US08922002B2

公开(公告)日：2014-12-30

申请号：US12796011

申请日：2010-06-08

申请人： Young Do Kweon ,  Tongbi Jiang

发明人： Young Do Kweon ,  Tongbi Jiang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/544 ,  H01L21/48

CPC分类号： H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/05599

摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

摘要翻译： 本文公开了在半导体工件上形成多个微电子器件的微电子器件和方法。 一种这样的方法包括将多个第一互连元件放置在半导体工件的一侧上，在工件侧面上形成层，通过加热第一互连元件来重塑第一互连元件，以及将多个第一互连元件的第一部分 单独的第二互连元件到相应的第一互连元件，其中所述单个第二互连元件的第二部分被暴露。