公开(公告)号：US09281286B1

公开(公告)日：2016-03-08

申请号：US14470679

申请日：2014-08-27

申请人： Weng F. Yap ,  Alan J. Magnus

发明人： Weng F. Yap ,  Alan J. Magnus

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/03 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/03466 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014

摘要： Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.

摘要翻译： 提供了微电子封装和用于制造具有纹理化焊盘的微电子封装的方法，其可以提高焊点可靠性。 在一个实施例中，该方法包括在下焊盘电介质层中形成具有纹理图案（例如阴影图案）的纹理化电介质区域。 在纹理化电介质区域上产生纹理化的焊盘。 纹理化焊料焊盘具有焊接接触表面，纹理图案被转印到该焊接接触表面，使得焊料接触表面的面积相对于等效尺寸的非变形焊料垫而增加。

公开(公告)号：US09997492B2

公开(公告)日：2018-06-12

申请号：US14086745

申请日：2013-11-21

申请人： Weng F. Yap ,  Scott M. Hayes ,  Alan J. Magnus

发明人： Weng F. Yap ,  Scott M. Hayes ,  Alan J. Magnus

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/94 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/00012

摘要： Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

公开(公告)号：US09502363B2

公开(公告)日：2016-11-22

申请号：US14223805

申请日：2014-03-24

申请人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US09281293B2

公开(公告)日：2016-03-08

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09401339B2

公开(公告)日：2016-07-26

申请号：US14277343

申请日：2014-05-14

申请人： Weng F. Yap ,  Alan J. Magnus

发明人： Weng F. Yap ,  Alan J. Magnus

IPC分类号： H01L23/52 ,  H01L23/00 ,  B23K1/20 ,  B23K1/00 ,  H01L23/31 ,  B23K3/06

CPC分类号： H01L24/20 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/02166 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13016 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/0132

摘要： Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

摘要翻译： 提供了晶圆级封装以及用于生产具有不可润湿的焊锡圈的晶片级封装的方法。 在一个实施例中，该方法包括在暴露焊料掩模层下面的图案化金属层的区域的焊料掩模层中形成焊接掩模开口。 在焊料掩模层中形成焊接掩模开口之前或之后，产生部分地在图案化金属层的暴露区域上延伸的不可润湿的焊接套环。 将焊球沉积在不可润湿的焊接环上并进入焊接掩模开口中，使得周边间隙设置在限定焊料掩模开口的焊料球的基部和焊料掩模层的侧壁周围。

公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09362234B2

公开(公告)日：2016-06-07

申请号：US14149335

申请日：2014-01-07

申请人： Eduard J. Pabst ,  Sergio P. Pacheco ,  Weng F. Yap

发明人： Eduard J. Pabst ,  Sergio P. Pacheco ,  Weng F. Yap

IPC分类号： H01L23/552 ,  H01L21/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L2223/6677 ,  H01L2224/12105

摘要： Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.

摘要翻译： 提供了屏蔽器件封装和相关的制造方法。 示例性的器件封装包括一个或多个电气部件，覆盖所述一个或多个电气部件的模制化合物，所述模制化合物内的导电互连结构，横向围绕所述一个或多个电部件和所述互连结构的导电框架结构，以及 覆盖一个或多个电气部件的屏蔽结构。 屏蔽结构电连接到框架结构，并且模制化合物的至少一部分位于屏蔽结构和一个或多个电气部件之间。

公开(公告)号：US09524950B2

公开(公告)日：2016-12-20

申请号：US13906621

申请日：2013-05-31

申请人： Weng F. Yap ,  Michael B. Vincent

发明人： Weng F. Yap ,  Michael B. Vincent

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC分类号： H01L24/97 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1815 ,  H01L2924/00

摘要： A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.

摘要翻译： 一种用于制造堆叠的微电子器件的方法包括将第一封装层附接到第二封装层以形成堆叠的微电子层。 第一包装层的锯街道覆盖并与第二包装层的锯切街道对齐。 第一和第二封装层包括形成在第一和第二封装层中的锯条和电子部件之间的相应的边缘连接器。 通过包装通孔形成在第一和第二包装层的锯条之一中。 通孔填充有导电材料。 堆叠的封装层沿着锯条街道以保持导电材料的一部分以在至少两个边缘连接器之间形成侧壁连接器的方式被切割。

公开(公告)号：US09257393B1

公开(公告)日：2016-02-09

申请号：US14500698

申请日：2014-09-29

申请人： Zhiwei Gong ,  Weng F. Yap

发明人： Zhiwei Gong ,  Weng F. Yap

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC分类号： H01L23/3114 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/78 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/29147 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.

摘要翻译： 提供扇出晶圆级封装（FO-WLP）和制造包含嵌入式地平线（EGP）和背面EGP互连结构的FO-WLP的方法。 在一个实施例中，该方法包括通过背面EGP互连结构将EGP电耦合到第一微电子器件的背面端子。 围绕第一微电子器件，EGP和EGP互连结构形成模制封装体。 模制包装体具有暴露EGP的前侧。 一个或多个再分配层形成在模制封装体的前侧，并且包含至少一个互连线，其通过EGP和背面EGP互连结构电耦合到背侧触点。

公开(公告)号：US09281284B2

公开(公告)日：2016-03-08

申请号：US14310992

申请日：2014-06-20

申请人： Weng F. Yap ,  Zhiwei Gong

发明人： Weng F. Yap ,  Zhiwei Gong

IPC分类号： H01L23/58 ,  H01L23/66 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/52 ,  H01L23/552

CPC分类号： H01L23/66 ,  H01L21/52 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6622 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3025

摘要： System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.

摘要翻译： 提供了系统级封装（SiP）和生产SiP的方法。 在一个实施例中，上述SiP制造方法包括在芯组件中形成通孔的步骤或工艺，所述芯组件包含暴露在通孔的侧壁表面处的电导通路径特征。 引线部件邻近芯部封装定位，使得引导部件的细长引线延伸到通孔中。 然后将诸如焊料的导电材料施加到通孔中以将引导部件的细长引线电耦合到芯部封装的导电路由特征。