公开(公告)号：US11699651B2

公开(公告)日：2023-07-11

申请号：US16167032

申请日：2018-10-22

Applicant: Applied Materials, Inc.

Inventor： Richard W. Plavidal ,  Albert Lan

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/373 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76841 ,  H01L23/3731 ,  H01L23/3732 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/81 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/13184 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/8113 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13157 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/00014

Abstract: Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

公开(公告)号：US20230197649A1

公开(公告)日：2023-06-22

申请号：US17913442

申请日：2020-05-28

Applicant: Mitsubishi Electric Corporation

Inventor： Yuji SATO

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/03 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/0603 ,  H01L2224/05557 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05671 ,  H01L2224/05186 ,  H01L2224/45147 ,  H01L2224/03614 ,  H01L2224/85 ,  H02M7/53871

Abstract: In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

公开(公告)号：US20230145031A1

公开(公告)日：2023-05-11

申请号：US17732324

申请日：2022-04-28

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Hua HU

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2924/35121 ,  H01L2224/8012 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03845 ,  H01L2224/08147 ,  H01L2224/05073 ,  H01L2224/05184 ,  H01L2224/05157 ,  H01L2224/05147 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05576 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/05681 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/05657 ,  H01L2224/05647 ,  H01L2224/05624

Abstract: A semiconductor structure, a method for forming a semiconductor structure, a stacked structure, and a wafer stacking method are provided. The semiconductor structure includes: a semiconductor substrate; a first dielectric layer on a surface of a semiconductor substrate; a top metal layer, in which the top metal layer is located in the first dielectric layer, and the top metal layer penetrates through the first dielectric layer; and a buffer layer located between the top metal layer and the first dielectric layer.

公开(公告)号：US20190237419A1

公开(公告)日：2019-08-01

申请号：US16383455

申请日：2019-04-12

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. ENQUIST

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/036 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/8019 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2224/29386 ,  H01L2924/053 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/01014 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/051 ,  H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US20190206919A1

公开(公告)日：2019-07-04

申请号：US16297167

申请日：2019-03-08

Applicant: SONY CORPORATION

Inventor： Masaki HANEDA

IPC: H01L27/146 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L27/14

CPC classification number: H01L27/14634 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L27/14 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05007 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/0801 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80009 ,  H01L2224/80097 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/0104 ,  H01L2924/05442 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

公开(公告)号：US20180019219A1

公开(公告)日：2018-01-18

申请号：US15545670

申请日：2015-02-25

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Kyu Oh Lee

IPC: H01L23/00 ,  B23K35/26 ,  H01L23/498 ,  C22C13/00 ,  C22C19/03

CPC classification number: H01L24/05 ,  B23K35/262 ,  C22C13/00 ,  C22C19/03 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05564 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/0568 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81444 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

公开(公告)号：US09779992B2

公开(公告)日：2017-10-03

申请号：US15013068

申请日：2016-02-02

Applicant: Renesas Electronics Corporation

Inventor： Ryohei Kitao ,  Yasuaki Tsuchiya

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L21/76898 ,  H01L21/02271 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/522 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.

公开(公告)号：US09679937B2

公开(公告)日：2017-06-13

申请号：US14992865

申请日：2016-01-11

Applicant: Sony Corporation

Inventor： Atsushi Okuyama

IPC: H01L23/00 ,  H01L27/146 ,  H01L25/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/14636 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/06 ,  H01L24/09 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14634 ,  H01L2224/05547 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0903 ,  H01L2224/095 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

公开(公告)号：US09589926B2

公开(公告)日：2017-03-07

申请号：US14931772

申请日：2015-11-03

Applicant: Fuji Electric Co., Ltd.

Inventor： Shoji Sakaguchi

IPC: B23K26/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/6835 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/741 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L29/417 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2224/03001 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/04026 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05255 ,  H01L2224/0539 ,  H01L2224/05393 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05755 ,  H01L2224/0589 ,  H01L2224/05893 ,  H01L2224/291 ,  H01L2224/741 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83894 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01046 ,  H01L2924/01005 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01006

Abstract: A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.

Abstract translation: 一种制造半导体器件的方法，包括：在一个主表面或另一个主表面上制备分别包括器件结构的一对衬底; 堆叠基板，使得所述一个主表面彼此面对，将所述另一表面暴露于外部，并且固定彼此堆叠的基板的整个周边外边缘; 然后电镀所述被堆叠和固定的基板的另一个主表面。

公开(公告)号：US09484316B2

公开(公告)日：2016-11-01

申请号：US14070334

申请日：2013-11-01

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。