Patent search ap:("Taiwan Semiconductor Manufacturing Company Page Ltd.") AND inv:"Shin-Puu Jeng"

71.

发明授权
Alignment mark design for packages 有权

公开(公告)号：US09666522B2

公开(公告)日：2017-05-30

申请号：US14465474

申请日：2014-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang , Hsien-Wei Chen , Ching-Wen Hsiao , Der-Chyang Yeh , Shin-Puu Jeng , Chen-Hua Yu

IPC: H01L21/56 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/544 , H01L21/48 , H01L23/538 , H01L21/683 , H01L25/10 , H01L25/00 , H01L25/065

CPC classification number: H01L23/544 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68318 , H01L2221/68372 , H01L2221/68381 , H01L2223/5442 , H01L2223/54426 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/83005 , H01L2224/83132 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1082 , H01L2924/00014 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/83 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

72.

发明申请
Bump Structure for Yield Improvement 审中-公开

公开(公告)号：US20170133346A1

公开(公告)日：2017-05-11

申请号：US15413058

申请日：2017-01-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Wei Chiu , Tzu-Yu Wang , Shang-Yun Hou , Shin-Puu Jeng , Hsien-Wei Chen , Hung-An Teng , Wei-Cheng Wu

IPC: H01L23/00 , H01L25/065 , C23C14/34 , C23C18/32 , C23C18/42 , C23C14/16 , H01L25/00 , B23K1/00

CPC classification number: H01L24/81 , B23K1/0016 , C23C14/165 , C23C14/34 , C23C18/32 , C23C18/42 , H01L23/3192 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/10125 , H01L2224/114 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/119 , H01L2224/11903 , H01L2224/13005 , H01L2224/13012 , H01L2224/13019 , H01L2224/13022 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13166 , H01L2224/13562 , H01L2224/13564 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/16058 , H01L2224/16059 , H01L2224/16145 , H01L2224/16148 , H01L2224/8112 , H01L2224/81141 , H01L2224/81193 , H01L2224/81345 , H01L2224/81365 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06593 , H01L2924/00014 , H01L2924/014 , H01L2924/13091 , H01L2224/81 , H01L2924/00012 , H01L2924/207 , H01L2924/206 , H01L2224/05552 , H01L2924/00

Abstract: A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

73.

发明申请
Cooling Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices 审中-公开

公开(公告)号：US20170103937A1

公开(公告)日：2017-04-13

申请号：US14880030

申请日：2015-10-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh , Chi-Hsi Wu , Shin-Puu Jeng , Tsung-Yu Chen , Wensen Hung

IPC: H01L23/427 , H01L21/56 , H01L23/367

CPC classification number: H01L23/4275 , H01L23/3128 , H01L23/3675 , H01L23/427 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/9222

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.

74.

发明申请
Chip-on-Substrate Packaging on Carrier 审中-公开

公开(公告)号：US20170098617A1

公开(公告)日：2017-04-06

申请号：US15379769

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu , Tzu-Shiun Sheu , Shin-Puu Jeng , Shih-Peng Tai , An-Jhih Su , Chi-Hsi Wu

IPC: H01L23/00 , H01L21/56 , H01L25/065 , H01L25/00 , H01L23/498 , H01L23/31 , H01L21/48 , H01L21/78

CPC classification number: H01L23/562 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L23/49827 , H01L24/02 , H01L24/03 , H01L24/16 , H01L24/80 , H01L24/81 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68331 , H01L2221/68381 , H01L2224/06181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/95 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555 , H01L2225/06562 , H01L2225/06582 , H01L2924/12042 , H01L2924/15159 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/83 , H01L2224/81

Abstract: A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

75.

发明申请
Wafer Level Package (WLP) and Method for Forming the Same 审中-公开

公开(公告)号：US20170092597A1

公开(公告)日：2017-03-30

申请号：US15376437

申请日：2016-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng , Hsien-Wen Liu

IPC: H01L23/00 , H01L21/02 , H01L23/538 , H01L23/31

CPC classification number: H01L23/564 , H01L21/02118 , H01L21/02164 , H01L21/0217 , H01L23/293 , H01L23/3171 , H01L23/3192 , H01L23/49811 , H01L23/49833 , H01L23/5389 , H01L24/05 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/105 , H01L2224/024 , H01L2224/03332 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/056 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/12105 , H01L2224/13022 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16238 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/18162 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H01L2924/00014 , H01L2924/014 , H01L2924/00012

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

76.

发明授权
Interposer test structures and methods 有权
Title translation: 内插测试结构和方法

公开(公告)号：US09589857B2

公开(公告)日：2017-03-07

申请号：US14846605

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng

IPC: H01L21/66 , G01R1/073 , H01L23/498 , H01L23/522 , H01L23/58 , H01L21/56 , H01L21/683

CPC classification number: H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract translation: 本公开的实施例是包括插入器的结构。插入器具有沿着插入件的周边延伸的测试结构，并且测试结构的至少一部分处于第一再分配元件中。第一再分配元件位于中介层的衬底的第一表面上。测试结构是中间的并且电耦合到至少两个探针焊盘。

77.

发明申请
3DIC Packages with Heat Dissipation Structures 审中-公开

公开(公告)号：US20160284670A1

公开(公告)日：2016-09-29

申请号：US15172330

申请日：2016-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wensen Hung , Szu-Po Huang , Kim Hong Chen , Shin-Puu Jeng

IPC: H01L25/065 , H01L23/367 , H01L25/00

CPC classification number: H01L25/0657 , H01L23/34 , H01L23/3672 , H01L23/3675 , H01L23/42 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H01L2924/00

Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM.

78.

发明授权
Chip packages and methods of manufacturing the same 有权
Title translation: 芯片封装及其制造方法

公开(公告)号：US09443806B2

公开(公告)日：2016-09-13

申请号：US14491507

申请日：2014-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng , Cheng-Chieh Hsieh , Tsung-Shu Lin , Chen-Hua Yu

IPC: H01L23/48 , H01L23/538 , H01L23/00 , H01L21/283 , H01L23/31 , H01L23/498

CPC classification number: H01L23/5389 , H01L21/283 , H01L23/00 , H01L23/3192 , H01L23/481 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/19 , H01L24/20 , H01L2224/0231 , H01L2224/02379 , H01L2224/12105 , H01L2224/18 , H01L2224/73267 , H01L2924/3512

Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a chip package may include: a chip having a contact pad disposed at a first side of the chip; a passivation layer over the first side of the chip, the passivation layer having an opening disposed over the contact pad; a polymer layer over the passivation layer, the polymer layer having an edge disposed over the contact pad; a conductive structure formed atop the contact pad, the conductive structure filling the opening of the passivation layer and covering the edge of the polymer layer; and a frontside redistribution layer (RDL) disposed over the conductive structure, the frontside RDL having a first portion electrically connected to the conductive structure and a second portion electrically connected to the first portion and extending laterally away from the first portion and the conductive structure.

Abstract translation: 公开了芯片封装及其制造方法。在一些实施例中，芯片封装可以包括：具有设置在芯片的第一侧的接触焊盘的芯片; 在所述芯片的第一侧上方的钝化层，所述钝化层具有设置在所述接触焊盘上的开口; 在所述钝化层上的聚合物层，所述聚合物层具有设置在所述接触焊盘上的边缘; 导电结构形成在接触垫顶部，导电结构填充钝化层的开口并覆盖聚合物层的边缘; 以及布置在所述导电结构上的前侧再分布层（RDL），所述前侧RDL具有电连接到所述导电结构的第一部分和与所述第一部分电连接并且横向远离所述第一部分和所述导电结构延伸的第二部分。