公开(公告)号：US11626341B2

公开(公告)日：2023-04-11

申请号：US17702817

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hui Wang ,  Der-Chyang Yeh ,  Shih-Peng Tai ,  Tsung-Shu Lin ,  Yi-Chung Huang

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A package structure includes a substrate, a semiconductor device and an adhesive layer. The semiconductor device is disposed on the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one of sides of the substrate, 0°

公开(公告)号：US20150221611A1

公开(公告)日：2015-08-06

申请号：US14257833

申请日：2014-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

Abstract translation: 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。

公开(公告)号：US09406650B2

公开(公告)日：2016-08-02

申请号：US14257833

申请日：2014-04-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC: H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

Abstract translation: 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。

公开(公告)号：US20150069580A1

公开(公告)日：2015-03-12

申请号：US14542317

申请日：2014-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

公开(公告)号：US11955401B2

公开(公告)日：2024-04-09

申请号：US18182364

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hui Wang ,  Der-Chyang Yeh ,  Shih-Peng Tai ,  Tsung-Shu Lin ,  Yi-Chung Huang

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/92225

Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle θ is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°

公开(公告)号：US20220216123A1

公开(公告)日：2022-07-07

申请号：US17702817

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hui Wang ,  Der-Chyang Yeh ,  Shih-Peng Tai ,  Tsung-Shu Lin ,  Yi-Chung Huang

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13

Abstract: A package structure includes a substrate, a semiconductor device and an adhesive layer. The semiconductor device is disposed on the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one of sides of the substrate, 0°

公开(公告)号：US09806062B2

公开(公告)日：2017-10-31

申请号：US15212782

申请日：2016-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/60 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit dies coupled to the substrate. The device also includes a molding material disposed over the substrate between adjacent ones of the plurality of integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies, wherein the cap layer comprises an electrically conductive material that directly contacts the molding material and each of the plurality of integrated circuit dies.

公开(公告)号：US20160329302A1

公开(公告)日：2016-11-10

申请号：US15212782

申请日：2016-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit dies coupled to the substrate. The device also includes a molding material disposed over the substrate between adjacent ones of the plurality of integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies, wherein the cap layer comprises an electrically conductive material that directly contacts the molding material and each of the plurality of integrated circuit dies.

Abstract translation: 封装的半导体器件被公开。 在一些实施例中，封装半导体器件包括衬底和耦合到衬底的多个集成电路管芯。 该装置还包括在多个集成电路管芯中相邻的集成电路管芯之间设置在衬底上的成型材料。 盖层设置在成型材料和多个集成电路管芯之上，其中盖层包括直接接触模制材料和多个集成电路管芯中的每一个的导电材料。

公开(公告)号：US20230215774A1

公开(公告)日：2023-07-06

申请号：US18182364

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hui Wang ,  Der-Chyang Yeh ,  Shih-Peng Tai ,  Tsung-Shu Lin ,  Yi-Chung Huang

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L24/81 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655

Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle θ is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°

公开(公告)号：US09478480B2

公开(公告)日：2016-10-25

申请号：US14542317

申请日：2014-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L23/48 ,  H01L21/683 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。