公开(公告)号：US20180130898A1

公开(公告)日：2018-05-10

申请号：US15604822

申请日：2017-05-25

申请人： Ideal Power, Inc.

发明人： Richard A. Blanchard ,  William C. Alexander

IPC分类号： H01L29/747 ,  H01L29/74 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/747 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66234 ,  H01L29/66295 ,  H01L29/66386 ,  H01L29/705 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7424

摘要： The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

公开(公告)号：US20180130785A1

公开(公告)日：2018-05-10

申请号：US15442592

申请日：2017-02-24

申请人： Samsung Electronics Co., Ltd.

发明人： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L23/532 ,  H01L29/47 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L27/0207 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/665

摘要： A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US20180114790A1

公开(公告)日：2018-04-26

申请号：US15839286

申请日：2017-12-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sheng-chen WANG ,  Sai-Hooi YEONG ,  Tsung-Chieh HSIAO

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161

CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes device areas where a Fin FET is disposed and a non-device area disposed between the device areas, which includes a dummy structure. The Fin FET includes a fin structure having a well region including a first semiconductor layer, a stressor region including a second semiconductor layer and a channel region including a third semiconductor layer; an isolation region in which the well region is embedded, and from which at least an upper port of the channel region is exposed; a gate structure disposed over a part of the fin structure. The dummy structure in the non-device area includes a first dummy layer formed over the first semiconductor layer and made of a different material from the stressor region, and a second dummy layer formed over the first dummy layer and made of a different material from the channel region.

公开(公告)号：US09954052B2

公开(公告)日：2018-04-24

申请号：US14958146

申请日：2015-12-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaehoon Lee

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L21/8238

CPC分类号： H01L29/0615 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/1054 ,  H01L29/16

摘要： A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.

公开(公告)号：US09953884B2

公开(公告)日：2018-04-24

申请号：US15353022

申请日：2016-11-16

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8258 ,  H01L21/8238 ,  H01L21/8252

CPC分类号： H01L21/8258 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02617 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8252 ,  H01L21/8256 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/7847 ,  H01L29/7849 ,  H01L29/785

摘要： In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

公开(公告)号：US09953710B2

公开(公告)日：2018-04-24

申请号：US15583411

申请日：2017-05-01

申请人： Micron Technology, Inc.

发明人： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC分类号： H01L29/66 ,  G11C16/14 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/792 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

摘要： Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US20180108736A1

公开(公告)日：2018-04-19

申请号：US15453118

申请日：2017-03-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Nicolas J. Loubet ,  Alexander Reznicek

IPC分类号： H01L29/10 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC分类号： H01L29/1079 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02483 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L29/0684 ,  H01L29/16 ,  H01L29/7849

摘要： A method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate. A rare earth oxide is grown and lattice matched to the lattice adjustment layer. A semiconductor layer is grown and lattice matched to the rare earth oxide and includes a same material as the semiconductor substrate such that the semiconductor layer is compressively strained.

公开(公告)号：US20180108526A1

公开(公告)日：2018-04-19

申请号：US15787605

申请日：2017-10-18

申请人： IMEC VZW

发明人： Jerome Mitard

IPC分类号： H01L21/02 ,  H01L29/06

CPC分类号： H01L21/02603 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0242 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775

摘要： The disclosed technology generally relates semiconductor devices and more particularly to semiconductor devices comprising nanowires. In one aspect, a method of fabricating a semiconductor device includes providing a semiconductor substrate having one or more elongated structures thereon and forming a strained layer of semiconductor material on at least one surface of the elongated structures, and annealing the strained layer to form a semiconductor nanowire.

公开(公告)号：US09947691B2

公开(公告)日：2018-04-17

申请号：US14435913

申请日：2014-08-15

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Xuebing Jiang ,  Lin Lin

IPC分类号： H01L27/12 ,  H01L21/77 ,  H01L29/786 ,  G02F1/1362 ,  H01L29/04 ,  H01L29/16 ,  H01L29/22 ,  H01L29/24 ,  H01L29/66

CPC分类号： H01L27/124 ,  G02F1/13624 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/16 ,  H01L29/22 ,  H01L29/24 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869

摘要： An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207) of the second TFT; a source electrode (206′) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.

公开(公告)号：US09941405B2

公开(公告)日：2018-04-10

申请号：US15340951

申请日：2016-11-01

申请人： Samsung Electronics Co., Ltd.

发明人： Jorge A. Kittl ,  Wei-E Wang ,  Mark S. Rodder

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L29/165 ,  H01L29/786

CPC分类号： H01L29/7848 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

摘要： A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.