公开(公告)号：US11087055B2

公开(公告)日：2021-08-10

申请号：US15985543

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Harsono S. Simka ,  Chris Bowen

IPC: G06F30/30 ,  H01L23/532 ,  H01L23/528 ,  G06F30/367 ,  G06F111/10

Abstract: A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.

公开(公告)号：US20190155977A1

公开(公告)日：2019-05-23

申请号：US15985543

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Harsono S. Simka ,  Chris Bowen

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/532

Abstract: A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.

公开(公告)号：US20180130785A1

公开(公告)日：2018-05-10

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L23/532 ,  H01L29/47 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/665

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US20170345932A1

公开(公告)日：2017-11-30

申请号：US15342008

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Chris Bowen ,  Kiyotaka Imai ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

公开(公告)号：US09773904B2

公开(公告)日：2017-09-26

申请号：US15132960

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Chris Bowen ,  Titash Rakshit ,  Palle Dharmendar ,  Mark Rodder

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7842 ,  H01L21/28247 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

公开(公告)号：US10510665B2

公开(公告)日：2019-12-17

申请号：US14931845

申请日：2015-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Mark Rodder ,  Jorge Kittl ,  Chris Bowen

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/225 ,  H01L21/768

Abstract: A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises a dielectric matrix having a first density. A dopant material layer is formed on the trench structure in which the dopant material layer comprises atoms of at least one of a rare-earth element. The ILD and the trench structure are annealed to form a dielectric matrix comprising a second density in one or more regions of the ILD on which the dopant material layer was formed that is greater than the first density. After annealing, the dielectric matrix comprising the second density includes increased bond lengths of oxygen-silicon bonds and/or oxygen-semiconductor bonds, increased bond angles of oxygen-silicon bonds and/or oxygen-semiconductor material bonds, and pores in the dielectric matrix are sealed compared to the dielectric matrix comprising the first density.

公开(公告)号：US10153368B2

公开(公告)日：2018-12-11

申请号：US15656898

申请日：2017-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Rwik Sengupta ,  Chris Bowen

IPC: H03K19/20 ,  H01L29/78 ,  H01L27/11

Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

公开(公告)号：US20170077304A1

公开(公告)日：2017-03-16

申请号：US15132960

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Chris Bowen ,  Titash Rakshit ,  Palle Dharmendar ,  Mark Rodder

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/28247 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

Abstract translation: 垂直场效应器件包括衬底和在衬底上包括In x Ga 1-x As的垂直沟道。 垂直通道包括从基板延伸并包括相对的垂直表面的支柱。 该装置还包括在垂直通道的相对的垂直表面上的应力层。 应力层包括外延形成在垂直通道上的外延晶体材料层，并且在垂直平面中具有与垂直沟道的相对垂直表面中的一个相垂直的晶格常数的晶格常数大于垂直沟道的对应晶格常数 渠道。

公开(公告)号：US10854591B2

公开(公告)日：2020-12-01

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/66

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US09728502B2

公开(公告)日：2017-08-08

申请号：US14920867

申请日：2015-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Mark Rodder ,  Rwik Sengupta ,  Chris Bowen

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.