公开(公告)号：US11158738B2

公开(公告)日：2021-10-26

申请号：US16548209

申请日：2019-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark Rodder ,  Vassilios Gerousis

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

Abstract: A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.

公开(公告)号：US10910313B2

公开(公告)日：2021-02-02

申请号：US15948543

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L23/535 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US09960232B2

公开(公告)日：2018-05-01

申请号：US15340775

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Titash Rakshit ,  Mark Rodder

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/20 ,  H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0665 ,  H01L21/30612 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/7783 ,  H01L29/78621 ,  H01L29/78681

Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

公开(公告)号：US20170323941A1

公开(公告)日：2017-11-09

申请号：US15340775

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Titash Rakshit ,  Mark Rodder

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/0665 ,  H01L21/30612 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/7783 ,  H01L29/78621 ,  H01L29/78681

Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

公开(公告)号：US10861950B2

公开(公告)日：2020-12-08

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/118

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US10510665B2

公开(公告)日：2019-12-17

申请号：US14931845

申请日：2015-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Mark Rodder ,  Jorge Kittl ,  Chris Bowen

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/225 ,  H01L21/768

Abstract: A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises a dielectric matrix having a first density. A dopant material layer is formed on the trench structure in which the dopant material layer comprises atoms of at least one of a rare-earth element. The ILD and the trench structure are annealed to form a dielectric matrix comprising a second density in one or more regions of the ILD on which the dopant material layer was formed that is greater than the first density. After annealing, the dielectric matrix comprising the second density includes increased bond lengths of oxygen-silicon bonds and/or oxygen-semiconductor bonds, increased bond angles of oxygen-silicon bonds and/or oxygen-semiconductor material bonds, and pores in the dielectric matrix are sealed compared to the dielectric matrix comprising the first density.

公开(公告)号：US09899529B2

公开(公告)日：2018-02-20

申请号：US15195886

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna Obradovic ,  Mark Rodder

IPC: H01L21/22 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/78642 ,  H01L21/2256 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.

公开(公告)号：US09653287B2

公开(公告)日：2017-05-16

申请号：US14919634

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark Rodder ,  Joon Hong ,  Jorge Kittl ,  Borna Obradovic

IPC: H01L21/02 ,  H01L29/417 ,  H01L29/786 ,  H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L21/285

CPC classification number: H01L21/02603 ,  H01L21/28518 ,  H01L21/28531 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696

Abstract: A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.

公开(公告)号：US20170077304A1

公开(公告)日：2017-03-16

申请号：US15132960

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Chris Bowen ,  Titash Rakshit ,  Palle Dharmendar ,  Mark Rodder

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/28247 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

Abstract translation: 垂直场效应器件包括衬底和在衬底上包括In x Ga 1-x As的垂直沟道。 垂直通道包括从基板延伸并包括相对的垂直表面的支柱。 该装置还包括在垂直通道的相对的垂直表面上的应力层。 应力层包括外延形成在垂直通道上的外延晶体材料层，并且在垂直平面中具有与垂直沟道的相对垂直表面中的一个相垂直的晶格常数的晶格常数大于垂直沟道的对应晶格常数 渠道。

公开(公告)号：US09570395B1

公开(公告)日：2017-02-14

申请号：US15158500

申请日：2016-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Mark Rodder

IPC: H01L23/02 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0665 ,  H01L29/785

Abstract: A semiconductor device includes: a substrate; a power rail on the substrate; an active layer on the substrate and at same layer as the power rail; and a contact electrically connecting the power rail to the active layer. The active layer includes source/drain terminals.

Abstract translation: 半导体器件包括：衬底; 基板上的电源轨; 在基板上并且与电力轨道相同层的有源层; 以及将电源轨电连接到有源层的触点。 有源层包括源极/漏极端子。