公开(公告)号：US11955534B2

公开(公告)日：2024-04-09

申请号：US18077142

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Joseph Steigerwald ,  Jinhong Shin ,  Vinay Chikarmane ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20240113119A1

公开(公告)日：2024-04-04

申请号：US18525988

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsu Ohtou ,  Ching-Wei Tsai ,  Jiun-Jia Huang ,  Kuan-Lun Cheng ,  Chi-Hsing Hsu

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

公开(公告)号：US11948941B2

公开(公告)日：2024-04-02

申请号：US17355206

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Tse Hung ,  Ang-Sheng Chou ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Chao-Ching Cheng

IPC: H01L29/417 ,  H01L21/8238 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/10 ,  H01L29/24

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/367 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41775

Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.

公开(公告)号：US20240096891A1

公开(公告)日：2024-03-21

申请号：US17946821

申请日：2022-09-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Chanro Park ,  Juntao Li

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A CMOS apparatus includes a semiconductor substrate that has a frontside and a backside opposite the frontside; a source/drain structure, which is disposed at the frontside of the substrate and has a backside that is adjacent to the substrate and a frontside that is opposite the backside of the source/drain structure; a backside interconnect layer, which is disposed at the backside of the substrate; a backside contact, which penetrates the substrate and electrically connects the source/drain structure to the backside interconnect layer; and a sigma-profiled dielectric structure that insulates first and second sides of the backside contact from the substrate.

公开(公告)号：US11935920B2

公开(公告)日：2024-03-19

申请号：US17874732

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/06 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H10B10/00

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H10B10/12

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US20240088225A1

公开(公告)日：2024-03-14

申请号：US18508788

申请日：2023-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Li-Heng Chen ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Ying-Lang Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

公开(公告)号：US11929423B2

公开(公告)日：2024-03-12

申请号：US17347715

申请日：2021-06-15

Applicant: Texas Instruments Incorporated

Inventor： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC: H01L29/66 ,  C01G55/00 ,  H01L21/02 ,  H01L21/263 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L29/49 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8238

CPC classification number: H01L29/665 ,  C01G55/00 ,  C01G55/004 ,  H01L21/02068 ,  H01L21/2633 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/31122 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/53242 ,  H01L24/00 ,  H01L28/24 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835

Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

公开(公告)号：US20240079466A1

公开(公告)日：2024-03-07

申请号：US18136975

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Baek ,  Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Hyumin Yoo ,  Namkyu Cho

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L2029/42388

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including, an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns.

公开(公告)号：US20240072115A1

公开(公告)日：2024-02-29

申请号：US18168504

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Xiang You ,  Wei-De Ho ,  Hsin Yang Hung ,  Meng-Yu Lin ,  Hsiang-Hung Huang ,  Chun-Fu Cheng ,  Kuan-Kan Hu ,  Szu-Hua Chen ,  Ting-Yun Wu ,  Wei-Cheng Tzeng ,  Wei-Cheng Lin ,  Cheng-Yin Wang ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.

公开(公告)号：US20240071836A1

公开(公告)日：2024-02-29

申请号：US17899111

申请日：2022-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chanro Park ,  Kangguo Cheng ,  Julien Frougier ,  Lawrence A. Clevenger

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure is presented including a first dielectric isolation pillar disposed between a pair of p-type field effect transistors (pFETs), a second dielectric isolation pillar disposed between a pair of n-type FETs (nFETs), a first source/drain (S/D) epi region having a first contact electrically connected to a backside power delivery network (BSPDN), the first contact being disposed on one side of the first dielectric isolation pillar, and a second S/D epi region having a second contact electrically connected to back-end-of-line (BEOL) components, the second contact being disposed on the other side of the first dielectric isolation pillar.