公开(公告)号：US09184112B1

公开(公告)日：2015-11-10

申请号：US14572950

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  Sebastian T. Ventrone

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/367 ,  H01L23/58 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L23/3171 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5384 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/922 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2924/00012

Abstract: A chip fabricated from a semiconductor material is disclosed. The chip may include active devices located below a first depth from a chip back side and a structure configured to remove heat from the chip. The structure may include microvias electrically insulated from the active devices and having a second depth, less than the first depth, from the back side towards the active devices. Each microvia may also have a fill material having a thermal conductivity greater than a semiconductor thermal conductivity. The structure may also include thermally conductive material regions on the back side of the chip in contact with sets of microvias. The structure may also include through-silicon vias electrically connected to the active devices, and extending from the back side to an active device side of the chip and configured to remove heat from the active devices to the back side of the chip.

Abstract translation: 公开了一种由半导体材料制成的芯片。 芯片可以包括位于从芯片背面的第一深度下方的有源器件和被配置为从芯片去除热量的结构。 该结构可以包括与有源器件电绝缘并且具有小于第一深度的从背侧朝向有源器件的第二深度的微孔。 每个微孔也可以具有导热率大于半导体热导率的填充材料。 该结构还可以包括在芯片的背面上与微孔组接触的导热材料区域。 该结构还可以包括电连接到有源器件的穿硅通孔，并且从芯片的背面延伸到有源器件侧并且被配置为将热量从有源器件移除到芯片的背面。

公开(公告)号：US20150048523A1

公开(公告)日：2015-02-19

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo SUGA ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L25/065 ,  B23K31/02 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  B23K37/04 ,  B23K37/00

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US08871611B2

公开(公告)日：2014-10-28

申请号：US14067453

申请日：2013-10-30

Applicant: Soitec

Inventor： Marcel Broekaart

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/762 ,  H01L27/146 ,  H01L27/14 ,  H01L21/67 ,  H01L21/20 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L21/76251 ,  H01L21/2003 ,  H01L21/67092 ,  H01L23/544 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14 ,  H01L27/14601 ,  H01L27/14687 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/8313 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure.

Abstract translation: 一种通过分子粘附将第一和第二晶片接合的方法。 该方法包括将晶片放置在具有大于预定阈值压力的第一压力（P1）的环境中，在该环境下，防止接合波传播的起始，使第一晶片和第二晶片对准和接触，并且自发地启动传播 只有通过将环境中的压力降低到低于阈值压力的第二压力（P2），晶片之间的结合波在它们接触之后。

公开(公告)号：US08501879B2

公开(公告)日：2013-08-06

申请号：US13221547

申请日：2011-08-30

Applicant: Kazunori Kondo ,  Michihiro Sugo ,  Hideto Kato

Inventor： Kazunori Kondo ,  Michihiro Sugo ,  Hideto Kato

IPC: C08G83/00 ,  C08G77/20 ,  C08L83/14 ,  C08F299/08

CPC classification number: H01L23/293 ,  C08G77/14 ,  C08G77/52 ,  C08L63/00 ,  C08L83/14 ,  C09J163/00 ,  C09J183/14 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3164 ,  H01L23/556 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/8113 ,  H01L2224/81193 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15788 ,  H05K3/305 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/00014

Abstract: A semiconductor apparatus adhesive composition having excellent adhesion properties when pressure-bonded and has excellent connection reliability and insulation reliability when hardened and an adhesive sheet using this adhesive composition. An adhesive composition including: (A) a silicone resin constituted of a repeating unit represented by the following general formula (1); (B) a thermosetting resin; and (C) a compound having a flux activity, where R1 to R4 represent univalent hydrocarbon groups having carbon numbers from 1 to 8, which are equal to or different from each other; each of l and m is an integer from 1 to 100; each of a, b, c, and d is 0 or a positive number and meets 0

Abstract translation: 一种半导体装置粘合剂组合物，当粘合时具有优异的粘合性能，并且当硬化时具有优异的连接可靠性和绝缘可靠性，以及使用该粘合剂组合物的粘合 一种粘合剂组合物，其包含：（A）由以下通式（1）表示的重复单元构成的有机硅树脂; （B）热固性树脂; 和（C）具有助焊剂活性的化合物，其中R 1至R 4表示碳数为1至8的一价烃基，它们彼此相同或不同; 1和m各自为1至100的整数; a，b，c和d中的每一个为0或正数，满足0 <（c + d）/（a + b + c + d） 并且X和Y各自为二价有机基团。

公开(公告)号：US08358015B2

公开(公告)日：2013-01-22

申请号：US13156941

申请日：2011-06-09

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Abstract translation: 分层芯片封装包括主体和布线。 主体包括：具有顶表面和底表面并且包括彼此堆叠的三个或更多个层部分的主要部分; 多个第一端子，设置在所述主要部件的顶表面上; 以及设置在主要部分的底表面上的多个第二端子。 每个层部分包括具有第一和第二表面的半导体芯片和电连接到布线的多个电极。 多个电极设置在半导体芯片的第一表面的一侧。 位于最靠近主要部分的顶表面的第一层部分和最靠近主要部分的底表面的第二层部分被布置成使得它们各自的半导体芯片的第二表面朝向彼此。 多个第一端子通过使用第一层部分的多个电极形成。 多个第二端子通过使用第二层部分的多个电极形成。

公开(公告)号：US08338266B2

公开(公告)日：2012-12-25

申请号：US13192312

申请日：2011-07-27

Applicant: Marcel Broekaart

Inventor： Marcel Broekaart

IPC: H01L21/46

CPC classification number: H01L21/76251 ,  H01L21/2003 ,  H01L21/67092 ,  H01L23/544 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14 ,  H01L27/14601 ,  H01L27/14687 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/8313 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

Abstract: The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

Abstract translation: 本发明涉及一种在至少第一晶片和第二晶片之间分子粘附的方法，包括使第一和第二晶片对齐，将第一和第二晶片置于具有大于预定阈值的第一压力（P1）的环境中 压力; 使第一晶片和第二晶片对准并接触; 以及在所述晶片对准之后，在所述第一和第二晶片之间启动粘结波的传播，并通过将所述环境内的压力降低到低于所述阈值压力的第二压力（P2）来接触。 本发明还涉及通过所述粘合粘合方法获得的三维复合结构。

公开(公告)号：US08283766B2

公开(公告)日：2012-10-09

申请号：US12874446

申请日：2010-09-02

Applicant: John A. Harada ,  David C. Douglas ,  Robert J. Drost

Inventor： John A. Harada ,  David C. Douglas ,  Robert J. Drost

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01L23/02

CPC classification number: H01L25/0657 ,  G02B6/43 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16135 ,  H01L2224/16151 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81141 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/819 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/1015 ,  H01L2924/10155 ,  H01L2924/151

Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

Abstract translation: 描述了斜坡堆叠芯片封装。 该芯片封装包括在水平方向彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的高带宽斜坡部件被电气和机械耦合到暴露的焊盘。 例如，斜坡部件可以使用：焊料，微弹簧和/或各向异性导电膜耦合到半导体管芯。 此外，每个半导体管芯包括静态弯曲部，使得每个半导体管芯的端部段平行于该方向，并机械耦合到斜坡部件。 这些端段可以促进芯片和斜坡部件之间的信号的高带宽通信，例如通过接近通信。

公开(公告)号：US08227927B2

公开(公告)日：2012-07-24

申请号：US12900190

申请日：2010-10-07

Applicant: Wei-Ming Chen ,  Shu-Ming Chang

Inventor： Wei-Ming Chen ,  Shu-Ming Chang

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/24051 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10S438/975 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 该封装包括载体衬底和其上至少两个半导体芯片。 每个半导体芯片包括多个导电焊盘。 位置结构设置在载体基板上以将半导体芯片的位置固定在载体基板上。 填充材料层形成在载体基板上，覆盖半导体芯片和位置结构，并且具有多个对应地暴露导电焊盘的开口。 再分配层（RDL）设置在填充材料层上并且通过多个开口连接到导电焊盘。 保护层覆盖填充材料层和RDL。 多个导电凸块设置在保护层上并与RDL电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US08203215B2

公开(公告)日：2012-06-19

申请号：US12835291

申请日：2010-07-13

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L23/48

CPC classification number: H01L23/522 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2746 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2221/68304

Abstract: A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip.

Abstract translation: 分层芯片封装包括主体和布线，所述布线包括设置在主体的侧表面上的多根布线。 主体包括主要部分和多个端子。 主要部分包括堆叠的多个层部分。 端子设置在主要部件的顶表面和底表面中的至少一个中并电连接到电线。 每个层部分包括半导体芯片和电连接到导线的多个电极。 电极包括旨在建立与半导体芯片的电连接的多个第一电极和不与半导体芯片接触的多个第二电极。 在至少一个层部分中，第一电极与半导体芯片接触并电连接。

公开(公告)号：US20120038027A1

公开(公告)日：2012-02-16

申请号：US13192312

申请日：2011-07-27

Applicant: Marcel Broekaart

Inventor： Marcel Broekaart

IPC: H01L21/30 ,  H01L29/06

CPC classification number: H01L21/76251 ,  H01L21/2003 ,  H01L21/67092 ,  H01L23/544 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14 ,  H01L27/14601 ,  H01L27/14687 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/8313 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

Abstract: The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

Abstract translation: 本发明涉及一种在至少第一晶片和第二晶片之间分子粘附的方法，包括使第一和第二晶片对齐，将第一和第二晶片置于具有大于预定阈值的第一压力（P1）的环境中 压力; 使第一晶片和第二晶片对准并接触; 以及在所述晶片对准之后，在所述第一和第二晶片之间启动粘结波的传播，并通过将所述环境内的压力降低到低于所述阈值压力的第二压力（P2）来接触。 本发明还涉及通过所述粘合粘合方法获得的三维复合结构。