公开(公告)号：US08410599B2

公开(公告)日：2013-04-02

申请号：US12756915

申请日：2010-04-08

Applicant: Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC: H01L23/04

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US08227927B2

公开(公告)日：2012-07-24

申请号：US12900190

申请日：2010-10-07

Applicant: Wei-Ming Chen ,  Shu-Ming Chang

Inventor： Wei-Ming Chen ,  Shu-Ming Chang

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/24051 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10S438/975 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 该封装包括载体衬底和其上至少两个半导体芯片。 每个半导体芯片包括多个导电焊盘。 位置结构设置在载体基板上以将半导体芯片的位置固定在载体基板上。 填充材料层形成在载体基板上，覆盖半导体芯片和位置结构，并且具有多个对应地暴露导电焊盘的开口。 再分配层（RDL）设置在填充材料层上并且通过多个开口连接到导电焊盘。 保护层覆盖填充材料层和RDL。 多个导电凸块设置在保护层上并与RDL电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US20110084382A1

公开(公告)日：2011-04-14

申请号：US12900190

申请日：2010-10-07

Applicant: Wei-Ming Chen ,  Shu-Ming Chang

Inventor： Wei-Ming Chen ,  Shu-Ming Chang

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/24051 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10S438/975 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 该封装包括载体衬底和其上至少两个半导体芯片。 每个半导体芯片包括多个导电焊盘。 位置结构设置在载体基板上以将半导体芯片的位置固定在载体基板上。 填充材料层形成在载体基板上，覆盖半导体芯片和位置结构，并且具有多个对应地暴露导电焊盘的开口。 再分配层（RDL）设置在填充材料层上并且通过多个开口连接到导电焊盘。 保护层覆盖填充材料层和RDL。 多个导电凸块设置在保护层上并与RDL电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US08564133B2

公开(公告)日：2013-10-22

申请号：US12860823

申请日：2010-08-20

Applicant: Ying-Nan Wen ,  Baw-Ching Perng ,  Wei-Ming Chen ,  Shu-Ming Chang

Inventor： Ying-Nan Wen ,  Baw-Ching Perng ,  Wei-Ming Chen ,  Shu-Ming Chang

IPC: H01L23/52

CPC classification number: H01L23/3135 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/24 ,  H01L24/28 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8314 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括具有上表面和相对的下表面的半导体衬底，穿过半导体衬底的上表面和下表面的通孔，设置在半导体衬底的上表面上的芯片，覆盖 所述通孔的侧壁电连接所述芯片，覆盖所述半导体衬底的上表面的第一绝缘层，覆盖所述半导体衬底的下表面的第二绝缘层和设置在所述半导体衬底的下表面上的接合结构 半导体衬底，其中所述第二绝缘层的材料与所述第一绝缘层的材料不同。

公开(公告)号：US08541877B2

公开(公告)日：2013-09-24

申请号：US12849089

申请日：2010-08-03

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC: H01L23/48

CPC classification number: H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US20100289092A1

公开(公告)日：2010-11-18

申请号：US12756915

申请日：2010-04-08

Applicant: Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

Inventor： Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC: H01L29/78 ,  H01L23/538

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US08310050B2

公开(公告)日：2012-11-13

申请号：US13024902

申请日：2011-02-10

Applicant: Wei-Ming Chen ,  Shu-Ming Chang

Inventor： Wei-Ming Chen ,  Shu-Ming Chang

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。 载体基板包括接地区域。 半导体芯片设置在载体基板的接地区域上。 每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。 填充材料层形成在载体衬底上并覆盖半导体芯片。 保护层覆盖填充层。 多个导电凸块设置在保护层的上方并与半导体芯片电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US20110140267A1

公开(公告)日：2011-06-16

申请号：US12849089

申请日：2010-08-03

Applicant: Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

Inventor： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US08674518B2

公开(公告)日：2014-03-18

申请号：US13340162

申请日：2011-12-29

Applicant: Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

Inventor： Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/498 ,  H01L21/00

CPC classification number: H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

公开(公告)号：US08624362B2

公开(公告)日：2014-01-07

申请号：US13219468

申请日：2011-08-26

Applicant: Yao-Hsiang Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Shu-Ming Chang

Inventor： Yao-Hsiang Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Shu-Ming Chang

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/71 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06155 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract translation: IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于 封装层的注入和形成在绝缘层的顶表面上并与用于电磁结构的集成电路层的焊盘电隔离的电磁屏蔽层。 因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。 此外，通孔的设计有助于进一步的包装过程。