公开(公告)号：US09082641B2

公开(公告)日：2015-07-14

申请号：US13897836

申请日：2013-05-20

Applicant: Semiconductor Manufacturing International Corporation (Shanghai)

Inventor： James Hong

IPC: H01L29/772 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a first barrier layer disposed on the substrate, a first dielectric layer disposed on the first barrier layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device further includes a third barrier layer and a first metal gate each being disposed between a first portion of the second barrier layer and a second portion of the second barrier layer. The first metal gate is disposed between the third barrier layer and the substrate. The semiconductor device further includes a second dielectric layer. The third barrier layer is disposed between the first metal gate and the second dielectric layer. The semiconductor device further includes a second metal gate. The semiconductor device further includes a contact hole positioned between the first metal gate and the second metal gate.

Abstract translation: 半导体器件包括衬底，设置在衬底上的第一势垒层，设置在第一阻挡层上的第一电介质层和设置在第一阻挡层上的第二势垒层。 半导体器件还包括第三阻挡层和第一金属栅极，每个第一栅极层和第一金属栅极分别设置在第二阻挡层的第一部分和第二阻挡层的第二部分之间。 第一金属栅极设置在第三阻挡层和基板之间。 半导体器件还包括第二介电层。 第三阻挡层设置在第一金属栅极和第二电介质层之间。 半导体器件还包括第二金属栅极。 半导体器件还包括位于第一金属栅极和第二金属栅极之间的接触孔。

公开(公告)号：US09054172B2

公开(公告)日：2015-06-09

申请号：US13705175

申请日：2012-12-05

Applicant: UNITED MICROELECTRNICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L29/772 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L23/532 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供了一种半导体结构，其包括衬底，晶体管，第一ILD层，第二ILD层，第一接触插塞，第二接触插塞和第三接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上。 第一接触插塞设置在第一ILD层中，并且第一接触插塞的顶表面高于栅极的顶表面。 第二ILD层设置在第一ILD层上。 第二接触插塞设置在第二ILD层中并电连接到第一接触插塞。 第三接触插塞设置在第一ILD层和第二ILD层中并且电连接到栅极。 本发明还提供了制备该方法的方法。

公开(公告)号：US09041103B2

公开(公告)日：2015-05-26

申请号：US13781722

申请日：2013-02-28

Applicant: Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Abstract translation: 即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻， 和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的 隔离墙和漂移区之间的电阻桥。 该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置 通过隔离壁耦合到掩埋层的漏极电压的百分比。

公开(公告)号：US09041056B2

公开(公告)日：2015-05-26

申请号：US13346906

申请日：2012-01-10

Applicant: Toshitaka Miyata ,  Kanna Adachi ,  Shigeru Kawanaka

Inventor： Toshitaka Miyata ,  Kanna Adachi ,  Shigeru Kawanaka

IPC: H01L29/16 ,  H01L29/772 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/772 ,  H01L29/0895 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7836

Abstract: According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.

Abstract translation: 根据一个实施例，一种半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极下方的栅极绝缘膜; 通过使用沟道层材料形成在所述栅极绝缘膜下方的沟道层; 源极区域和漏极区域，形成在所述基板中，以在沟道方向上插入所述沟道层; 以及源极延伸层，其形成在沟道层和源极区域之间的衬底中，以与沟道层的源极侧端部重叠。 源延伸层与沟道层形成异质界面。 异步接口是一个用于载波的隧道通道。

公开(公告)号：USRE45462E1

公开(公告)日：2015-04-14

申请号：US13569604

申请日：2012-08-08

Applicant: Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

Inventor： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

IPC: H01L29/78 ,  H01L29/772

CPC classification number: H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

Abstract translation: 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。

公开(公告)号：US08981467B2

公开(公告)日：2015-03-17

申请号：US13909963

申请日：2013-06-04

Applicant: SK hynix Inc.

Inventor： Jung Woo Park

IPC: H01L29/772 ,  H01L29/78 ,  H01L27/108

CPC classification number: H01L29/7827 ,  H01L27/10873

Abstract: A semiconductor device includes an active region including a surface region and a first recess formed on both sides of the surface region, the active region extending along a first direction; a device isolation structure surrounding the active region; a pair of gate lines extending along the surface region of the active region in a second direction perpendicular to the first direction; a plurality of second recesses formed in the device isolation structure beneath the gate lines and including given portions of the gate lines filled into the second recesses; a plurality of first junction regions formed in the active region beneath the first recesses; and a second junction region formed in the surface region between the gate lines, wherein the second junction region defines at least two vertical-type channels below the gate line with the plurality of first junction regions.

Abstract translation: 半导体器件包括有源区，其包括表面区域和形成在表面区域的两侧上的第一凹部，所述有源区域沿着第一方向延伸; 包围有源区的器件隔离结构; 一对栅极线，沿着与第一方向垂直的第二方向沿有源区的表面区域延伸; 多个第二凹部，其形成在所述栅极线下方的所述器件隔离结构中，并且包括填充到所述第二凹槽中的所述栅极线的给定部分; 形成在所述第一凹部下方的所述有源区域中的多个第一接合区域; 以及形成在所述栅极线之间的表面区域中的第二结区，其中所述第二结区在所述栅极线的下方限定与所述多个第一结区相对应的至少两个垂直型沟道。

公开(公告)号：US20150043114A1

公开(公告)日：2015-02-12

申请号：US14454435

申请日：2014-08-07

Applicant: Fairchild Semiconductor Corporation

Inventor： Tirthajyoti SARKAR ,  Adrian MIKOLAJCZAK ,  Ihsiu HO ,  Ashok CHALLA

IPC: H01L27/02 ,  H01L29/772 ,  H02H9/04 ,  H01L29/40

CPC classification number: H01L27/027 ,  H01L27/0266 ,  H01L27/0288 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/407 ,  H01L29/408 ,  H01L29/6606 ,  H01L29/66166 ,  H01L29/772 ,  H01L29/8605 ,  H01L29/861

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Abstract translation: 在一个一般方面，装置可以包括半导体衬底和限定在半导体衬底内并具有沿着垂直轴线对准的深度，沿着纵向轴线对准的长度和沿着水平轴线对齐的宽度的沟槽。 该设备包括设置在沟槽内的电介质和设置在电介质内并通过电介质与半导体衬底绝缘的电极。 半导体衬底可以具有垂直且与沟槽相邻的部分，并且半导体衬底的部分可以具有沿沟槽的整个深度连续的导电类型。 该装置被偏置到常开状态。

公开(公告)号：US08941175B2

公开(公告)日：2015-01-27

申请号：US13918994

申请日：2013-06-17

Applicant: United Microelectronics Corp.

Inventor： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC: H01L29/06 ,  H01L29/772 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract translation: 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

公开(公告)号：US20150008445A1

公开(公告)日：2015-01-08

申请号：US14496140

申请日：2014-09-25

Applicant: International Rectifier Corporation

Inventor： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC: H01L25/07 ,  H01L29/16 ,  H01L29/772 ,  H01L23/00 ,  H01L29/20

CPC classification number: H01L25/074 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/69 ,  H01L24/72 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/772 ,  H01L29/778 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract translation: 一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。 封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。 封装的第三端子耦合到FET的源极。 以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

公开(公告)号：US08896067B2

公开(公告)日：2014-11-25

申请号：US13736111

申请日：2013-01-08

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  David Vaclav Horak ,  Shom Ponoth ,  Chih-Chao Yang ,  Charles William Koburger, III

IPC: H01L29/772 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/785

Abstract: Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.

Abstract translation: 本发明的实施例提供一种在基板上形成第一组翅片和第二组翅片的方法; 用第一介电材料覆盖第一和第二组翅片的顶部第一部分; 用第二电介质材料覆盖第一和第二组翅片的底部第二部分，第一组的底部第二部分和具有相同高度的第二组翅片; 将第一组翅片和第二组翅片的中间第三部分暴露于氧化环境以产生将顶部第一部分与第一组翅片和第二组鳍片的底部第二部分分离的氧化物部分; 以及使用所述第一和第二组翅片的顶部第一部分在所述一个或多个FinFET的栅极下形成翅片形成一个或多个鳍状场效应晶体管（FinFET）。