公开(公告)号：US09773808B2

公开(公告)日：2017-09-26

申请号：US14705778

申请日：2015-05-06

Applicant: Honeywell International Inc.

Inventor： Paul S. Fechner

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L49/02 ,  H01L21/762 ,  H01L27/07 ,  H01L29/10 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/76283 ,  H01L27/0738 ,  H01L27/0883 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/66166 ,  H01L29/78606 ,  H01L29/8605

Abstract: This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming agate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.

公开(公告)号：US20170263602A1

公开(公告)日：2017-09-14

申请号：US15592256

申请日：2017-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsin HU ,  Hsueh-Shih Fan ,  Huan-Tsung Huang

IPC: H01L27/06 ,  H01L29/16 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/2053 ,  H01L21/76895 ,  H01L21/823431 ,  H01L23/535 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66166 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.

公开(公告)号：US20170133461A1

公开(公告)日：2017-05-11

申请号：US15409065

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L27/098

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US20170018658A1

公开(公告)日：2017-01-19

申请号：US15121879

申请日：2014-07-14

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/8605 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

Abstract translation: 对于基于鳍的电子器件描述了固体源极扩散结。 在一个示例中，在基板上形成翅片。 第一掺杂剂类型的玻璃沉积在衬底上并且在鳍的下部上方。 在衬底和鳍上沉积一层第二掺杂剂类型。 将玻璃退火以将掺杂剂驱动到翅片和基底中。 去除玻璃并且在翅片之上形成第一和第二接触件，而不接触翅片的下部。

公开(公告)号：US20150349046A1

公开(公告)日：2015-12-03

申请号：US14287434

申请日：2014-05-27

Applicant: Texas Instruments Incorporated

Inventor： Stephen Keith Heinrich-Barna ,  Douglas P. Verret ,  Alwin J. Tsao

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L27/06 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L28/20 ,  H01L21/26513 ,  H01L21/31053 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/0802 ,  H01L29/0649 ,  H01L29/66166 ,  H01L29/8605

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract translation: 包含阱电阻器的集成电路在阱电阻器中具有STI场氧化物和电阻器虚设有源区。 STI沟槽被蚀刻并填充沟槽填充电介质材料。 通过CMP工艺从有源区域上去除沟槽填充介电材料，在STI沟槽中留下STI场氧化物。 随后，将掺杂剂注入到阱电阻器区域中的衬底中以形成阱电阻器。 包含多晶硅电阻器的集成电路在多晶硅电阻器的区域中具有STI场氧化物和电阻器虚设有源区域。 通过CMP工艺形成并平坦化多晶硅层。 在CMP平坦化的多晶硅层上形成多晶硅蚀刻掩模以限定多晶硅电阻。 多晶硅蚀刻工艺在由多晶硅蚀刻掩模暴露的区域中去除多晶硅，留下多晶硅电阻器。

公开(公告)号：US20150043114A1

公开(公告)日：2015-02-12

申请号：US14454435

申请日：2014-08-07

Applicant: Fairchild Semiconductor Corporation

Inventor： Tirthajyoti SARKAR ,  Adrian MIKOLAJCZAK ,  Ihsiu HO ,  Ashok CHALLA

IPC: H01L27/02 ,  H01L29/772 ,  H02H9/04 ,  H01L29/40

CPC classification number: H01L27/027 ,  H01L27/0266 ,  H01L27/0288 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/407 ,  H01L29/408 ,  H01L29/6606 ,  H01L29/66166 ,  H01L29/772 ,  H01L29/8605 ,  H01L29/861

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Abstract translation: 在一个一般方面，装置可以包括半导体衬底和限定在半导体衬底内并具有沿着垂直轴线对准的深度，沿着纵向轴线对准的长度和沿着水平轴线对齐的宽度的沟槽。 该设备包括设置在沟槽内的电介质和设置在电介质内并通过电介质与半导体衬底绝缘的电极。 半导体衬底可以具有垂直且与沟槽相邻的部分，并且半导体衬底的部分可以具有沿沟槽的整个深度连续的导电类型。 该装置被偏置到常开状态。

公开(公告)号：US20150035012A1

公开(公告)日：2015-02-05

申请号：US14486405

申请日：2014-09-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Yao Lai ,  Yen-Ming Chen ,  Shyh-Wei Wang

IPC: H01L29/737 ,  H01L21/265 ,  H01L21/283 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/265 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66166 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/8605

Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

Abstract translation: 公开了双极结型晶体管（BJT）的方法和装置。 BJT包括由p型半导体材料制成的集电体，在集电体上由n型阱制成的基座; 以及发射极，其包括在基极上的p +区和p +区上的SiGe层。 BJT可以通过提供包括收集器，集电器上的基底，在基底上形成牺牲层的半导体衬底来形成，在牺牲层上图案化第一光致抗蚀剂以暴露由基底内的STI包围的开口; 将p型材料通过牺牲层注入到基底的区域中，从p型植入物形成p +区; 在蚀刻的p +区上形成SiGe层以形成发射极。 通过在牺牲层上图案化第一光致抗蚀剂的步骤，可以共享制造多晶硅晶体管的过程。

公开(公告)号：US08487294B2

公开(公告)日：2013-07-16

申请号：US13129815

申请日：2010-06-30

Applicant: Dianzhong Wen ,  Xiaohui Bai

Inventor： Dianzhong Wen ,  Xiaohui Bai

IPC: H01L45/00

CPC classification number: H01L29/66166 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/55 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.

Abstract translation: 纳米结构快速开关忆阻器包括上电极，下电极和设置在上电极和下电极之间的三层纳米膜。 三层纳米膜由N型半导体层，N型半导体层上的中性半导体层和中性半导体层上的P型半导体层组成。 本发明的纳米结构快开式忆阻器具有开关速度快，制造方法简单，制造成本低的优点。

公开(公告)号：US08048800B2

公开(公告)日：2011-11-01

申请号：US12603766

申请日：2009-10-22

Applicant: Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min ,  Wan-Joo Kim

Inventor： Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min ,  Wan-Joo Kim

IPC: H01L21/44 ,  H01L21/311

CPC classification number: H01L29/6609 ,  H01L21/30625 ,  H01L29/66083 ,  H01L29/66166 ,  H01L29/66174

Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.

Abstract translation: 公开了一种使用沟槽技术制造二端子半导体部件的方法，包括通过蚀刻形成在其上生长有杂质添加的有源层的基板上形成的蚀刻图案来形成沟槽，在正面上方形成前金属层 在去除蚀刻图案之后，通过使用蒸镀法或溅射法形成基板的表面，在其上形成有前金属层的基板的前表面上形成金属镀层，使用在 至少一种机械抛光方法和化学抛光方法，直到暴露前金属层，在抛光的基底上形成后金属层，并且通过使用干蚀刻方法和湿蚀刻方法中的至少一种来去除每个部件。

公开(公告)号：US20110059609A1

公开(公告)日：2011-03-10

申请号：US12603766

申请日：2009-10-22

Applicant: Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min

Inventor： Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min

IPC: H01L21/283

CPC classification number: H01L29/6609 ,  H01L21/30625 ,  H01L29/66083 ,  H01L29/66166 ,  H01L29/66174

Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.

Abstract translation: 公开了一种使用沟槽技术制造二端子半导体部件的方法，包括通过蚀刻形成在其上生长有杂质添加的有源层的基板上形成的蚀刻图案来形成沟槽，在正面上方形成前金属层 在去除蚀刻图案之后，通过使用蒸镀法或溅射法形成基板的表面，在其上形成有前金属层的基板的前表面上形成金属镀层，使用在 至少一种机械抛光方法和化学抛光方法，直到暴露前金属层，在抛光的基底上形成后金属层，并且通过使用干蚀刻方法和湿蚀刻方法中的至少一种来去除每个部件。