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    Methods and apparatus for bipolar junction transistors and resistors
    2.
    发明授权
    Methods and apparatus for bipolar junction transistors and resistors 有权
    双极结晶体管和电阻器的方法和装置

    公开(公告)号：US09184265B2

    公开(公告)日：2015-11-10

    申请号：US14486405

    申请日：2014-09-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Yao Lai ,  Yen-Ming Chen ,  Shyh-Wei Wang

    IPC: H01L21/02 ,  H01L29/737 ,  H01L29/66 ,  H01L29/8605 ,  H01L21/265 ,  H01L21/283 ,  H01L29/165 ,  H01L29/06

    CPC classification number: H01L29/737 ,  H01L21/265 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66166 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/8605

    Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

    Abstract translation: 公开了双极结型晶体管（BJT）的方法和装置。 BJT包括由p型半导体材料制成的集电体，在集电体上由n型阱制成的基座; 以及发射极，其包括在基极上的p +区和p +区上的SiGe层。 BJT可以通过提供包括收集器，集电器上的基底，在基底上形成牺牲层的半导体衬底来形成，在牺牲层上图案化第一光致抗蚀剂以暴露由基底内的STI包围的开口; 将p型材料通过牺牲层注入到基底的区域中，从p型植入物形成p +区; 在蚀刻的p +区上形成SiGe层以形成发射极。 通过在牺牲层上图案化第一光致抗蚀剂的步骤，可以共享制造多晶硅晶体管的过程。

    Methods and Apparatus for Bipolar Junction Transistors and Resistors
    6.
    发明申请
    Methods and Apparatus for Bipolar Junction Transistors and Resistors 审中-公开
    双极结晶体管和电阻器的方法和装置

    公开(公告)号：US20150035012A1

    公开(公告)日：2015-02-05

    申请号：US14486405

    申请日：2014-09-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Yao Lai ,  Yen-Ming Chen ,  Shyh-Wei Wang

    IPC: H01L29/737 ,  H01L21/265 ,  H01L21/283 ,  H01L29/165 ,  H01L29/66

    CPC classification number: H01L29/737 ,  H01L21/265 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66166 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/8605

    Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

    Abstract translation: 公开了双极结型晶体管（BJT）的方法和装置。 BJT包括由p型半导体材料制成的集电体，在集电体上由n型阱制成的基座; 以及发射极，其包括在基极上的p +区和p +区上的SiGe层。 BJT可以通过提供包括收集器，集电器上的基底，在基底上形成牺牲层的半导体衬底来形成，在牺牲层上图案化第一光致抗蚀剂以暴露由基底内的STI包围的开口; 将p型材料通过牺牲层注入到基底的区域中，从p型植入物形成p +区; 在蚀刻的p +区上形成SiGe层以形成发射极。 通过在牺牲层上图案化第一光致抗蚀剂的步骤，可以共享制造多晶硅晶体管的过程。

    Integrated circuits and manufacturing methods thereof
    9.
    发明授权
    Integrated circuits and manufacturing methods thereof 有权
    集成电路及其制造方法

    公开(公告)号：US09385213B2

    公开(公告)日：2016-07-05

    申请号：US13722142

    申请日：2012-12-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chung-Cheng Wu ,  Ali Keshavarzi ,  Ka Hing Fung ,  Ta-Pen Guo ,  Jiann-Tyng Tzeng ,  Yen-Ming Chen ,  Shyue-Shyh Lin ,  Shyh-Wei Wang ,  Sheng-Jier Yang ,  Hsiang-Jen Tseng ,  David B. Scott ,  Min Cao

    IPC: H01L21/336 ,  H01L29/66 ,  H01L23/485 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

    CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/7848 ,  H01L2224/16225

    Abstract: A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

    Abstract translation: 一种形成集成电路的方法，包括在衬底上形成第一扩散区域和第二扩散区域，其中所述第一扩散区域被配置为用于第一类型晶体管，所述第二扩散区域被配置为用于第二类型晶体管。 该方法还包括在第一扩散区域中形成第一源区和漏区。 该方法还包括在第二扩散区域中形成第二源区和漏区。 该方法还包括形成跨越第一扩散区域和第二扩散区域延伸的栅电极。 该方法还包括形成第一金属层，第二金属层和第三金属层。 第一金属层与第一源区电耦合。 第二金属层与第一和第二漏极区域电耦合。 第三金属层与第二源极区域电耦合。

    STRAINED ASYMMETRIC SOURCE/DRAIN
    10.
    发明申请
    STRAINED ASYMMETRIC SOURCE/DRAIN 有权
    应变不对称源/排水

    公开(公告)号：US20150179760A1

    公开(公告)日：2015-06-25

    申请号：US14585934

    申请日：2014-12-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chun-Fai Cheng ,  Chin-Te Su ,  Ka-Hing Fung ,  Shyh-Wei Wang

    IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

    Abstract: The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes receiving a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

    Abstract translation: 本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。 制造半导体器件的方法包括接收衬底并在衬底上形成多晶硅叠层。 掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。 邻近衬底上的多晶硅叠层形成间隔物。 源极区和漏极区被蚀刻在衬底中。 应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。 多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

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