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公开(公告)号：US12057419B2
公开(公告)日：2024-08-06
申请号：US17874036
申请日：2022-07-26
发明人： Chih-Fan Huang , Mao-Nan Wang , Hui-Chi Chen , Dian-Hau Chen , Yen-Ming Chen
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/13 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/03462 , H01L2224/0401 , H01L2224/05548 , H01L2224/13016
摘要： A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.
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公开(公告)号：US20230389447A1
公开(公告)日：2023-11-30
申请号：US18446563
申请日：2023-08-09
发明人： Tsung-Chieh Hsiao , Po-Sheng Lu , Wei-Chih Wen , Liang-Wei Wang , Yu-Jen Wang , Dian-Hau Chen , Yen-Ming Chen
摘要： A method of forming a semiconductor device includes providing a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.
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公开(公告)号：US20230387183A1
公开(公告)日：2023-11-30
申请号：US18358557
申请日：2023-07-25
发明人： Chih-Fan Huang , Hsiang-Ku Shen , Dian-Hau Chen , Yen-Ming Chen
IPC分类号： H10N79/00 , H01L21/285 , H01L27/07 , H01L27/10 , H01L27/06 , H01L21/321
CPC分类号： H01L28/24 , H01L21/28531 , H01L27/0794 , H01L27/101 , H01L27/0676 , H01L27/0682 , H01L21/3212
摘要： Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.
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公开(公告)号：US20230386940A1
公开(公告)日：2023-11-30
申请号：US17824263
申请日：2022-05-25
发明人： Chih-Hsin Yang , Dian-Hau Chen , Yen-Ming Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12
摘要： A method for forming a semiconductor structure is provided. The method includes forming an interconnect structure, and forming a conductive feature electrically connected to the interconnect structure. The method also includes forming a first passivation layer over the interconnect structure and the conductive feature, and etching the first passivation layer to form an opening that exposes the conductive feature. The method further includes performing an electrical test on the conductive feature, filling the opening with an oxide material, and attaching a carrier substrate over the oxide material using a bonding layer.
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公开(公告)号：US20230062842A1
公开(公告)日：2023-03-02
申请号：US17460627
申请日：2021-08-30
发明人： Chih-Fan Huang , Wen-Chiung Tu , Liang-Wei Wang , Dian-Hau Chen , Yen-Ming Chen
摘要： Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.
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公开(公告)号：US11569236B2
公开(公告)日：2023-01-31
申请号：US17106880
申请日：2020-11-30
发明人： Hung-Li Chiang , Cheng-Yi Peng , Tsung-Yao Wen , Yee-Chia Yeo , Yen-Ming Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L21/3105 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L29/08
摘要： A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
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公开(公告)号：US11569130B2
公开(公告)日：2023-01-31
申请号：US17031023
申请日：2020-09-24
发明人： Tzung-Yi Tsai , Yen-Ming Chen , Tsung-Lin Lee , Chih-Chieh Yeh
IPC分类号： H01L21/8234 , H01L27/088
摘要： A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
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公开(公告)号：US11538927B2
公开(公告)日：2022-12-27
申请号：US17336673
申请日：2021-06-02
IPC分类号： H01L29/66 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8234
摘要： Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.
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公开(公告)号：US11362199B2
公开(公告)日：2022-06-14
申请号：US16382860
申请日：2019-04-12
发明人： I-Hsieh Wong , Yen-Ting Chen , Wei-Yang Lee , Feng-Cheng Yang , Yen-Ming Chen
IPC分类号： H01L29/66 , H01L29/08 , H01L29/78 , H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/306
摘要： In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
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公开(公告)号：US11296077B2
公开(公告)日：2022-04-05
申请号：US16429253
申请日：2019-06-03
发明人： Yen-Ting Chen , Bo-Yu Lai , Chien-Wei Lee , Hsueh-Chang Sung , Wei-Yang Lee , Feng-Cheng Yang , Yen-Ming Chen
IPC分类号： H01L27/088 , H01L29/66 , H01L29/06 , H01L29/78 , H01L29/161 , H01L21/02 , H01L21/8234 , H01L21/3065
摘要： A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.
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