JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE
    2.
    发明申请
    JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE 有权
    无连接绝缘栅极电流限制器件

    公开(公告)号:US20150043114A1

    公开(公告)日:2015-02-12

    申请号:US14454435

    申请日:2014-08-07

    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

    Abstract translation: 在一个一般方面,装置可以包括半导体衬底和限定在半导体衬底内并具有沿着垂直轴线对准的深度,沿着纵向轴线对准的长度和沿着水平轴线对齐的宽度的沟槽。 该设备包括设置在沟槽内的电介质和设置在电介质内并通过电介质与半导体衬底绝缘的电极。 半导体衬底可以具有垂直且与沟槽相邻的部分,并且半导体衬底的部分可以具有沿沟槽的整个深度连续的导电类型。 该装置被偏置到常开状态。

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