公开(公告)号：US20090321798A1

公开(公告)日：2009-12-31

申请号：US12553408

申请日：2009-09-03

Applicant: Dae Hong MIN

Inventor： Dae Hong MIN

IPC: H01L31/112

CPC classification number: H01L27/14632 ,  H01L27/14687 ,  Y10S438/981

Abstract: Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process.

Abstract translation: 公开了CMOS传感器和制造CMOS传感器的方法。 该方法包括以下步骤：在包括单元区域和划线区域的半导体衬底的整个表面上形成第一USG层; 掩蔽单元区域，然后移除在划线区域上形成的第一USG层; 在半导体衬底的整个表面上形成SiN层; 掩蔽细胞区域，然后除去形成在划线区域上的SiN层; 在所述半导体衬底的整个表面上形成第二USG层; 并掩蔽划线区域，然后去除在单元区域上形成的第二USG层。 USG层仅形成在没有SiN层的划线层上，使得SiN颗粒在烧结过程中不会落到USG层上。

公开(公告)号：US07550378B2

公开(公告)日：2009-06-23

申请号：US11616275

申请日：2006-12-26

Applicant: Dae Hong Min

Inventor： Dae Hong Min

IPC: H01L21/4763

CPC classification number: H01L21/76819 ,  H01L21/31053

Abstract: A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area. An insulating layer is deposited over the semiconductor substrate. The insulating layer is planarized through a chemical mechanical polishing (CMP) process including a first polishing step and a second polishing step having different removal rates with respect to the insulating layer formed over the cell area and the scribe area.

Abstract translation: 一种制造半导体器件的方法，包括提供包括形成有相对高的器件元件密度的单元区域的半导体衬底和形成有低于单元区域的器件元件密度的器件元件密度的划线区域。 绝缘层沉积在半导体衬底上。 通过化学机械抛光（CMP）工艺对绝缘层进行平面化处理，该工艺包括第一抛光步骤和第二抛光步骤，所述第一抛光步骤和第二抛光步骤相对于在单元区域和划刻区域上形成的绝缘层具有不同的去除速率。

公开(公告)号：US07605016B2

公开(公告)日：2009-10-20

申请号：US11646797

申请日：2006-12-27

Applicant: Dae Hong Min

Inventor： Dae Hong Min

IPC: H01L21/00

CPC classification number: H01L27/14632 ,  H01L27/14687 ,  Y10S438/981

Abstract: Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process.

Abstract translation: 公开了CMOS传感器和制造CMOS传感器的方法。 该方法包括以下步骤：在包括单元区域和划线区域的半导体衬底的整个表面上形成第一USG层; 掩蔽单元区域，然后移除在划线区域上形成的第一USG层; 在半导体衬底的整个表面上形成SiN层; 掩蔽细胞区域，然后除去形成在划线区域上的SiN层; 在所述半导体衬底的整个表面上形成第二USG层; 并掩蔽划线区域，然后去除在单元区域上形成的第二USG层。 USG层仅形成在没有SiN层的划线层上，使得SiN颗粒在烧结过程中不会落到USG层上。

公开(公告)号：US20070148969A1

公开(公告)日：2007-06-28

申请号：US11616275

申请日：2006-12-26

Applicant: Dae Hong Min

Inventor： Dae Hong Min

IPC: H01L21/461

CPC classification number: H01L21/76819 ,  H01L21/31053

Abstract: A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area. An insulating layer is deposited over the semiconductor substrate. The insulating layer is planarized through a chemical mechanical polishing (CMP) process including a first polishing step and a second polishing step having different removal rates with respect to the insulating layer formed over the cell area and the scribe area.

Abstract translation: 一种制造半导体器件的方法，包括提供包括形成有相对高的器件元件密度的单元区域的半导体衬底和形成有低于单元区域的器件元件密度的器件元件密度的划线区域。 绝缘层沉积在半导体衬底上。 通过化学机械抛光（CMP）工艺对绝缘层进行平面化处理，该工艺包括第一抛光步骤和第二抛光步骤，所述第一抛光步骤和第二抛光步骤相对于在单元区域和划刻区域上形成的绝缘层具有不同的去除速率。

公开(公告)号：US08048800B2

公开(公告)日：2011-11-01

申请号：US12603766

申请日：2009-10-22

Applicant: Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min ,  Wan-Joo Kim

Inventor： Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min ,  Wan-Joo Kim

IPC: H01L21/44 ,  H01L21/311

CPC classification number: H01L29/6609 ,  H01L21/30625 ,  H01L29/66083 ,  H01L29/66166 ,  H01L29/66174

Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.

Abstract translation: 公开了一种使用沟槽技术制造二端子半导体部件的方法，包括通过蚀刻形成在其上生长有杂质添加的有源层的基板上形成的蚀刻图案来形成沟槽，在正面上方形成前金属层 在去除蚀刻图案之后，通过使用蒸镀法或溅射法形成基板的表面，在其上形成有前金属层的基板的前表面上形成金属镀层，使用在 至少一种机械抛光方法和化学抛光方法，直到暴露前金属层，在抛光的基底上形成后金属层，并且通过使用干蚀刻方法和湿蚀刻方法中的至少一种来去除每个部件。

公开(公告)号：US20110059609A1

公开(公告)日：2011-03-10

申请号：US12603766

申请日：2009-10-22

Applicant: Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min

Inventor： Jin-Koo Rhee ,  Seong-Dae Lee ,  Mi-Ra Kim ,  Dae-Hong Min

IPC: H01L21/283

CPC classification number: H01L29/6609 ,  H01L21/30625 ,  H01L29/66083 ,  H01L29/66166 ,  H01L29/66174

Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.

Abstract translation: 公开了一种使用沟槽技术制造二端子半导体部件的方法，包括通过蚀刻形成在其上生长有杂质添加的有源层的基板上形成的蚀刻图案来形成沟槽，在正面上方形成前金属层 在去除蚀刻图案之后，通过使用蒸镀法或溅射法形成基板的表面，在其上形成有前金属层的基板的前表面上形成金属镀层，使用在 至少一种机械抛光方法和化学抛光方法，直到暴露前金属层，在抛光的基底上形成后金属层，并且通过使用干蚀刻方法和湿蚀刻方法中的至少一种来去除每个部件。