公开(公告)号：US08389366B2

公开(公告)日：2013-03-05

申请号：US12129840

申请日：2008-05-30

Applicant: Won Gi Min ,  Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/772

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).

Abstract translation: 即使当主体（44,44'，84,84“），RESURF装置（40,60,80,80'，80”），例如LDMOS晶体管也通过小心的电荷平衡来增强击穿电压BVdss并导通电阻， ）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且延伸通过相同的导电类型 至少进入下面的主体区域（44,44'，84,84'）中的漂移区域（50,50'，90,90'），和/或（ii）将偏置Viso施加到周围的侧向掺杂隔离壁（102 ）和/或（iii）在所述隔离壁（102）和所述漂移区域（50,50'，90,90'）之间提供可变电阻桥（104）。 桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制 电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

公开(公告)号：US20090294849A1

公开(公告)日：2009-12-03

申请号：US12129840

申请日：2008-05-30

Applicant: Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L23/58

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).

Abstract translation: 即使在主体（44,44'，84,84）中，分解电压BVdss被增强，并且RESURF器件（40,60,80,80'，80“）中的导通电阻降低，例如LDMOS晶体管 '）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且具有相同的导电类型延伸 至少穿过所述漂移区域（50,50'，90,90'）到所述下部体区域（44,44'，84,84'）中，和/或（ii）将偏压Viso施加到周围的侧向掺杂隔离壁 102）和/或（iii）在隔离壁（102）和漂移区域（50,50'，90,90'）之间提供可变电阻桥（104） 。 桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制 电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

公开(公告)号：US09041103B2

公开(公告)日：2015-05-26

申请号：US13781722

申请日：2013-02-28

Applicant: Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Abstract translation: 即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻， 和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的 隔离墙和漂移区之间的电阻桥。 该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置 通过隔离壁耦合到掩埋层的漏极电压的百分比。

公开(公告)号：US09136323B2

公开(公告)日：2015-09-15

申请号：US14486104

申请日：2014-09-15

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract translation: 制造晶体管的方法包括在衬底中形成场隔离区域。 在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。 漏极区形成在衬底的第二区域中。 第一和第二区域横向重叠以限定晶体管的导电路径。 第一区域不横向跨越第二区域延伸。

公开(公告)号：US20150004768A1

公开(公告)日：2015-01-01

申请号：US14486104

申请日：2014-09-15

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract translation: 制造晶体管的方法包括在衬底中形成场隔离区域。 在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。 漏极区形成在衬底的第二区域中。 第一和第二区域横向重叠以限定晶体管的导电路径。 第一区域不横向跨越第二区域延伸。

公开(公告)号：US20130292764A1

公开(公告)日：2013-11-07

申请号：US13465761

申请日：2012-05-07

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract translation: 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

公开(公告)号：US08853780B2

公开(公告)日：2014-10-07

申请号：US13465761

申请日：2012-05-07

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/66

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract translation: 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

公开(公告)号：US07608513B2

公开(公告)日：2009-10-27

申请号：US11626928

申请日：2007-01-25

Applicant: Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

IPC: H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

Abstract translation: 描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。 横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。 第一栅极（G1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分覆盖两者。 与G1（56）间隔开的第二门（G2）（66）覆盖在N阱（44）上。 衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。 当身体接触（74）连接到G2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg2提供给G2（66）。 所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

公开(公告)号：US07795674B2

公开(公告)日：2010-09-14

申请号：US12560588

申请日：2009-09-16

Applicant: Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

Abstract: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Abstract translation: N沟道器件的一个实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。 横向隔离壁围绕衬底的至少一部分并且与孔间隔开。 第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。 与第一个门相隔开的第二个栅极覆盖着N阱。 与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。 当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

公开(公告)号：US20100213570A1

公开(公告)日：2010-08-26

申请号：US12392641

申请日：2009-02-25

Applicant: Won Gi Min ,  Geoffrey W. Perkins ,  Kyle D. Zukowski ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Geoffrey W. Perkins ,  Kyle D. Zukowski ,  Jiang-Kai Zuo

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An antifuse (40, 80, 90′) comprises, first (22′, 24′) and second (26′) conductive regions having spaced-apart curved portions (55, 56), with a first dielectric region (44) therebetween, forming in combination with the curved portions (55, 56) a curved breakdown region (47) adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region (42) is desirably provided adjacent the breakdown region (47) to inhibit heat loss from the breakdown region (47) during programming. Lower programming voltages and currents are observed compared to antifuses (30) using substantially planar dielectric regions (32). In a further embodiment, a resistive region (922) is inserted in one lead (92, 92′) of the antifuses (90, 90′) with either planar (37) or curved (47) breakdown regions to improve post-programming sense reliability.

Abstract translation: 反熔丝（40,80,90'）包括具有间隔开的弯曲部分（55,56）的第一（22'，24'）和第二（26'）导电区域，其间具有第一介电区域（44） 与所述弯曲部分（55,56）组合形成弯曲击穿区域（47），所述弯曲击穿区域（47）响应于预定编程电压而适于从基本上不导电的初始状态切换到基本上导通的最终状态。 使用小于编程电压的感测电压来确定反熔丝的状态为OFF（高阻抗）或ON（低阻抗）。 希望在击穿区域（47）附近提供浅沟槽隔离（STI）区域（42），以在编程期间抑制来自击穿区域（47）的热损失。 与使用基本平坦的电介质区域（32）的反熔丝（30）相比，观察到较低的编程电压和电流。 在另一个实施例中，电阻区域（922）被插入到具有平面（37）或弯曲（47）击穿区域的反熔丝（90,90'）的一个引线（92,92'）中，以改善后编程感 可靠性。