公开(公告)号：US20100025765A1

公开(公告)日：2010-02-04

申请号：US12560588

申请日：2009-09-16

Applicant: Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

Abstract: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Abstract translation: N沟道器件的实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。 横向隔离壁围绕衬底的至少一部分并且与孔间隔开。 第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。 与第一个门相隔开的第二个栅极覆盖着N阱。 与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。 当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

公开(公告)号：US20080182394A1

公开(公告)日：2008-07-31

申请号：US11626928

申请日：2007-01-25

Applicant: Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

IPC: H01L21/04

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

Abstract translation: 描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。 横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。 第一栅极（G 1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分地覆盖两者。 与G 1（56）间隔开的第二栅极（G 2）（66）覆盖在N阱（44）上。 衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。 当主体接触件（74）连接到G 2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg 2提供给G 2（66）。 所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

公开(公告)号：US07608513B2

公开(公告)日：2009-10-27

申请号：US11626928

申请日：2007-01-25

Applicant: Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

IPC: H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

Abstract translation: 描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。 横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。 第一栅极（G1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分覆盖两者。 与G1（56）间隔开的第二门（G2）（66）覆盖在N阱（44）上。 衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。 当身体接触（74）连接到G2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg2提供给G2（66）。 所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

公开(公告)号：US06667500B2

公开(公告)日：2003-12-23

申请号：US10126562

申请日：2002-04-19

Applicant: Thierry Sicard ,  Veronique C. Macary

Inventor： Thierry Sicard ,  Veronique C. Macary

IPC: H01L2976

CPC classification number: H01L27/0266

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

公开(公告)号：US06413806B1

公开(公告)日：2002-07-02

申请号：US09510814

申请日：2000-02-23

Applicant: Thierry Sicard ,  Veronique C. Macary

Inventor： Thierry Sicard ,  Veronique C. Macary

IPC: H01L21336

CPC classification number: H01L27/0266

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract translation: LDMOS场效应晶体管（80）提供保护以防止施加在器件上的电压的极性的无意的反转。 为了保护N沟道器件，围绕漏极区域（32）提供浮动P型阻挡区域（82）。 阻挡区域（82）与形成晶体管（80）的扩散通道（34）的体区（28）间隔开。 第一栅电极（36）控制扩散通道（34）的导电性，第二栅电极（84）控制阻挡区域（82）的表面（35）的导电性。

公开(公告)号：US07795674B2

公开(公告)日：2010-09-14

申请号：US12560588

申请日：2009-09-16

Applicant: Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Won Gi Min ,  Jiang-Kai Zuo

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7831

Abstract: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Abstract translation: N沟道器件的一个实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。 横向隔离壁围绕衬底的至少一部分并且与孔间隔开。 第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。 与第一个门相隔开的第二个栅极覆盖着N阱。 与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。 当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

公开(公告)号：US20100164056A1

公开(公告)日：2010-07-01

申请号：US12717522

申请日：2010-03-04

Applicant: Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

IPC: H01L29/06

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract translation: 提供了微电子组件的实施例。 第一和第二半导体器件形成在具有第一浓度的第一掺杂剂类型的衬底上。 具有第二掺杂剂类型的第一和第二掩埋区分别形成在第一和第二半导体器件的下面，其间具有间隙。 至少一个阱区形成在衬底上并且在第一和第二半导体器件之间。 具有第二浓度的第一掺杂剂类型的屏障区域形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得至少一部分阻挡区域从第一和第二半导体器件的深度延伸大于或等于 埋藏区域的深度。

公开(公告)号：US20080203519A1

公开(公告)日：2008-08-28

申请号：US11680316

申请日：2007-02-28

Applicant: Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493

Abstract: A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the first and second semiconductor devices with a gap (34) therebetween. At least one well region (64, 70) is formed over the substrate and between the first and second semiconductor devices. A barrier region (48) having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth (82) from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract translation: 提供了一种用于形成微电子组件和微电子组件的方法。 第一和第二半导体器件（72）形成在具有第一浓度的第一掺杂剂类型的衬底（20）上。 具有第二掺杂剂类型的第一和第二埋入区域（28）分别在第一和第二半导体器件的下方形成，其间具有间隙（34）。 在衬底上以及第一和第二半导体器件之间形成至少一个阱区（64,70）。 具有第二浓度的第一掺杂剂类型的势垒区域（48）形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得阻挡区域的至少一部分从第一和第二半导体器件延伸深度（82） 大于或等于埋藏区域的深度。

公开(公告)号：US20080166849A1

公开(公告)日：2008-07-10

申请号：US11650188

申请日：2007-01-04

Applicant: Hongning Yang ,  Veronique C. Macary ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Veronique C. Macary ,  Jiang-Kai Zuo

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7835

Abstract: An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.

Abstract translation: 描述了具有非常轻掺杂的衬底（42）的N沟道器件（40,60），其中设置有间隔开的P（46）和N（44）阱，其侧边缘（461,45）延伸到 表面（47）。 栅极（56）覆盖在P（46）和N（44）孔之间的表面（47）上。 与源极（50）相邻的P阱边缘（461）基本上与左边缘边缘（561）对准。 所述N阱边缘（45）位于所述右边缘边缘（562）内或所述右边缘边缘（562）中，所述右边缘边缘（562）与所述漏极（48）间隔开第一距离（471）。 N阱（44）期望地包括与漏极（48）欧姆接触的较重的掺杂区域（62），并且其左边缘（621）位于右栅极边缘（562）和漏极（48）之间的大约一半处 ）。 使用门（56）作为掩模，将HALO注入口袋（52）设置在左门边缘（561）下方。 所得到的器件（40,60）在较高电压下工作，Rdson较低，HCI较少，非常低的截止状态泄漏。 P和N掺杂剂互换以提供P沟道器件。

公开(公告)号：US07795702B2

公开(公告)日：2010-09-14

申请号：US12717522

申请日：2010-03-04

Applicant: Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

IPC: H01L29/00

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract translation: 提供了微电子组件的实施例。 第一和第二半导体器件形成在具有第一浓度的第一掺杂剂类型的衬底上。 具有第二掺杂剂类型的第一和第二掩埋区分别形成在第一和第二半导体器件的下面，其间具有间隙。 至少一个阱区形成在衬底上并且在第一和第二半导体器件之间。 具有第二浓度的第一掺杂剂类型的屏障区域形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得至少一部分阻挡区域从第一和第二半导体器件的深度延伸大于或等于 埋藏区域的深度。