公开(公告)号：US09041103B2

公开(公告)日：2015-05-26

申请号：US13781722

申请日：2013-02-28

Applicant: Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Abstract translation: 即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻， 和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的 隔离墙和漂移区之间的电阻桥。 该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置 通过隔离壁耦合到掩埋层的漏极电压的百分比。

公开(公告)号：US08389366B2

公开(公告)日：2013-03-05

申请号：US12129840

申请日：2008-05-30

Applicant: Won Gi Min ,  Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/772

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).

Abstract translation: 即使当主体（44,44'，84,84“），RESURF装置（40,60,80,80'，80”），例如LDMOS晶体管也通过小心的电荷平衡来增强击穿电压BVdss并导通电阻， ）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且延伸通过相同的导电类型 至少进入下面的主体区域（44,44'，84,84'）中的漂移区域（50,50'，90,90'），和/或（ii）将偏置Viso施加到周围的侧向掺杂隔离壁（102 ）和/或（iii）在所述隔离壁（102）和所述漂移区域（50,50'，90,90'）之间提供可变电阻桥（104）。 桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制 电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

公开(公告)号：US20090294849A1

公开(公告)日：2009-12-03

申请号：US12129840

申请日：2008-05-30

Applicant: Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L23/58

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).

Abstract translation: 即使在主体（44,44'，84,84）中，分解电压BVdss被增强，并且RESURF器件（40,60,80,80'，80“）中的导通电阻降低，例如LDMOS晶体管 '）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且具有相同的导电类型延伸 至少穿过所述漂移区域（50,50'，90,90'）到所述下部体区域（44,44'，84,84'）中，和/或（ii）将偏压Viso施加到周围的侧向掺杂隔离壁 102）和/或（iii）在隔离壁（102）和漂移区域（50,50'，90,90'）之间提供可变电阻桥（104） 。 桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制 电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

公开(公告)号：US09136323B2

公开(公告)日：2015-09-15

申请号：US14486104

申请日：2014-09-15

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract translation: 制造晶体管的方法包括在衬底中形成场隔离区域。 在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。 漏极区形成在衬底的第二区域中。 第一和第二区域横向重叠以限定晶体管的导电路径。 第一区域不横向跨越第二区域延伸。

公开(公告)号：US20150004768A1

公开(公告)日：2015-01-01

申请号：US14486104

申请日：2014-09-15

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract translation: 制造晶体管的方法包括在衬底中形成场隔离区域。 在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。 漏极区形成在衬底的第二区域中。 第一和第二区域横向重叠以限定晶体管的导电路径。 第一区域不横向跨越第二区域延伸。

公开(公告)号：US08853780B2

公开(公告)日：2014-10-07

申请号：US13465761

申请日：2012-05-07

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/66

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract translation: 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

公开(公告)号：US20130292764A1

公开(公告)日：2013-11-07

申请号：US13465761

申请日：2012-05-07

Applicant: Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract translation: 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

公开(公告)号：US08487398B2

公开(公告)日：2013-07-16

申请号：US12835900

申请日：2010-07-14

Applicant: Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

Inventor： Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L21/70

CPC classification number: H01L29/94 ,  H01L29/66181

Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Abstract translation: 半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型 第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。 该装置可以方便地连接到边缘电容器。

公开(公告)号：US20100301403A1

公开(公告)日：2010-12-02

申请号：US12475232

申请日：2009-05-29

Applicant: WON GI MIN ,  John L. Huber ,  Jiang-Kai Zuo

Inventor： WON GI MIN ,  John L. Huber ,  Jiang-Kai Zuo

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404

Abstract: A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.

Abstract translation: 半导体器件包括半导体衬底内的源极区域，半导体衬底内的漏极区域，半导体衬底上的控制栅极以及源极区域和漏极区域之间的控制栅极，控制栅极和漏极区域之间的第一栅极，以及 半导体区域内和控制栅极与第一栅极之间的第一掺杂区域。 形成半导体器件的方法可以包括在半导体衬底上沉积电极材料，图案化电极材料以形成控制栅极和第一栅极，在控制栅极和第一栅极之间注入半导体衬底内的第一掺杂区域，同时 使用控制栅极和第一栅极作为掩模，并且在半导体衬底内注入源极区域。

公开(公告)号：US07795702B2

公开(公告)日：2010-09-14

申请号：US12717522

申请日：2010-03-04

Applicant: Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

Inventor： Won Gi Min ,  Veronique C. Macary ,  Jiang-Kai Zuo

IPC: H01L29/00

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract translation: 提供了微电子组件的实施例。 第一和第二半导体器件形成在具有第一浓度的第一掺杂剂类型的衬底上。 具有第二掺杂剂类型的第一和第二掩埋区分别形成在第一和第二半导体器件的下面，其间具有间隙。 至少一个阱区形成在衬底上并且在第一和第二半导体器件之间。 具有第二浓度的第一掺杂剂类型的屏障区域形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得至少一部分阻挡区域从第一和第二半导体器件的深度延伸大于或等于 埋藏区域的深度。