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    Semiconductor device having vertical-type channel
    1.
    发明授权
    Semiconductor device having vertical-type channel 有权
    具有垂直型通道的半导体器件

    公开(公告)号：US08981467B2

    公开(公告)日：2015-03-17

    申请号：US13909963

    申请日：2013-06-04

    申请人： SK hynix Inc.

    发明人： Jung Woo Park

    IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L27/108

    CPC分类号： H01L29/7827 ,  H01L27/10873

    摘要： A semiconductor device includes an active region including a surface region and a first recess formed on both sides of the surface region, the active region extending along a first direction; a device isolation structure surrounding the active region; a pair of gate lines extending along the surface region of the active region in a second direction perpendicular to the first direction; a plurality of second recesses formed in the device isolation structure beneath the gate lines and including given portions of the gate lines filled into the second recesses; a plurality of first junction regions formed in the active region beneath the first recesses; and a second junction region formed in the surface region between the gate lines, wherein the second junction region defines at least two vertical-type channels below the gate line with the plurality of first junction regions.

    摘要翻译： 半导体器件包括有源区，其包括表面区域和形成在表面区域的两侧上的第一凹部，所述有源区域沿着第一方向延伸; 包围有源区的器件隔离结构; 一对栅极线，沿着与第一方向垂直的第二方向沿有源区的表面区域延伸; 多个第二凹部，其形成在所述栅极线下方的所述器件隔离结构中，并且包括填充到所述第二凹槽中的所述栅极线的给定部分; 形成在所述第一凹部下方的所述有源区域中的多个第一接合区域; 以及形成在所述栅极线之间的表面区域中的第二结区，其中所述第二结区在所述栅极线的下方限定与所述多个第一结区相对应的至少两个垂直型沟道。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11895828B2

    公开(公告)日：2024-02-06

    申请号：US17719990

    申请日：2022-04-13

    申请人： SK hynix Inc.

    发明人： Jae Man Yoon ,  Jin Hwan Jeon ,  Tae Kyun Kim ,  Jung Woo Park ,  Su Ock Chung ,  Jae Won Ha

    IPC分类号： H10B12/00

    CPC分类号： H10B12/482 ,  H10B12/0335

    摘要： A semiconductor device and a method of fabricating the same are provided. According to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.