公开(公告)号：US09607727B2

公开(公告)日：2017-03-28

申请号：US14733281

申请日：2015-06-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sein Chang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01B1/00 ,  H01B1/12 ,  H01B1/22 ,  H01L23/00 ,  H01L23/373 ,  H01L23/492

CPC classification number: H01B1/22 ,  H01L23/3733 ,  H01L23/4922 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/0132 ,  H01L2924/06 ,  H01L2924/069 ,  H01L2924/1426 ,  H01L2924/2064

Abstract: An anisotropic electroconductive particle including a first insulating layer, a first conductive layer disposed on the first insulating layer, and a second insulating layer disposed on the first conductive layer.

公开(公告)号：US20170084577A1

公开(公告)日：2017-03-23

申请号：US15364715

申请日：2016-11-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Michael J. SEDDON

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08137 ,  H01L2224/11002 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16137 ,  H01L2224/16147 ,  H01L2224/24051 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/29019 ,  H01L2224/29021 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/30151 ,  H01L2224/32137 ,  H01L2224/73251 ,  H01L2224/73267 ,  H01L2224/80897 ,  H01L2224/809 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2224/821 ,  H01L2224/82121 ,  H01L2224/82138 ,  H01L2224/82203 ,  H01L2224/82815 ,  H01L2224/82862 ,  H01L2224/82874 ,  H01L2224/83141 ,  H01L2224/83203 ,  H01L2224/839 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10156 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15159 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/03 ,  H05K3/4661 ,  H05K3/4664 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/08 ,  H01L2224/24 ,  H01L2224/83 ,  H01L2924/014

Abstract: A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component. The 3D semiconductor package can be formed with multiple tiers of vertical components and horizontal components.

公开(公告)号：US09601448B2

公开(公告)日：2017-03-21

申请号：US15094759

申请日：2016-04-08

Applicant: Waseda University

Inventor： Kohei Tatsumi

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L21/52 ,  H01L23/498

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/76 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05173 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05673 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13411 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24225 ,  H01L2224/24245 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/29012 ,  H01L2224/29017 ,  H01L2224/29147 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40991 ,  H01L2224/40996 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48873 ,  H01L2224/48991 ,  H01L2224/48996 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/75754 ,  H01L2224/76754 ,  H01L2224/81002 ,  H01L2224/81205 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81473 ,  H01L2224/81815 ,  H01L2224/8184 ,  H01L2224/81901 ,  H01L2224/8192 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82399 ,  H01L2224/83002 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83473 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83901 ,  H01L2224/8392 ,  H01L2224/8492 ,  H01L2224/85205 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/9201 ,  H01L2924/00011 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01045 ,  H01L2224/18 ,  H01L2224/24 ,  H01L2224/82 ,  H01L2224/83205

Abstract: An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

公开(公告)号：US20170028477A1

公开(公告)日：2017-02-02

申请号：US15302712

申请日：2015-04-10

Applicant: Alpha Metals, Inc.

Inventor： Rohan P. Setna ,  Nirmalya Kumar Chaki ,  Poulami Sengupta Roy ,  Siuli Sarkar ,  Sutapa Mukherjee

IPC: B22F9/24 ,  B22F1/02 ,  B22F9/04 ,  H01L23/00 ,  C09J9/02 ,  C09J11/04 ,  C09C1/62 ,  B22F1/00 ,  C09J1/00

CPC classification number: B22F9/24 ,  B22F1/0014 ,  B22F1/0074 ,  B22F1/025 ,  B22F9/04 ,  B22F2009/043 ,  B22F2301/10 ,  B22F2301/255 ,  C01P2004/20 ,  C01P2004/32 ,  C01P2004/51 ,  C01P2004/61 ,  C01P2006/11 ,  C01P2006/12 ,  C01P2006/80 ,  C09C1/62 ,  C09C1/622 ,  C09C1/627 ,  C09J1/00 ,  C09J9/02 ,  C09J11/04 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/111 ,  H01L2224/1111 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11438 ,  H01L2224/1144 ,  H01L2224/11505 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13387 ,  H01L2224/1339 ,  H01L2224/13439 ,  H01L2224/1349 ,  H01L2224/13499 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/271 ,  H01L2224/2711 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27438 ,  H01L2224/2744 ,  H01L2224/27505 ,  H01L2224/29011 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29439 ,  H01L2224/2949 ,  H01L2224/29499 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8184 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/8384 ,  H01L2224/94 ,  H01L2924/12041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Abstract translation: 一种制造金属粉末的方法，包括：提供碱金属盐溶液; 使碱金属盐溶液与还原剂接触以从其中沉淀金属粉末; 并从溶剂中回收沉淀的金属粉末。

公开(公告)号：US20170025377A1

公开(公告)日：2017-01-26

申请号：US15121855

申请日：2015-02-26

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

Inventor： Paul GONDCHARTON ,  Lamine BENAISSA ,  Bruno IMBERT ,  Hubert MORICEAU

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/2745 ,  H01L2224/2755 ,  H01L2224/27845 ,  H01L2224/29147 ,  H01L2224/80055 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8092 ,  H01L2224/80948 ,  H01L2224/83895 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01008 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/00012

Abstract: A method for producing a structure by direct bonding of two elements, the method including: production of the elements to be assembled and assembly of the elements. The production of the elements to be assembled includes: deposition on a substrate of a TiN layer by physical vapor deposition, and deposition of a copper layer on the TiN layer. The assembly of the elements includes: polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, bringing the surfaces into contact, and storing the structure at atmospheric pressure and at ambient temperature.

Abstract translation: 一种用于通过直接粘合两个元件来生产结构的方法，所述方法包括：生产要组装的元件和元件的组装。 要组装的元件的生产包括：通过物理气相沉积在TiN层的衬底上沉积，并且在TiN层上沉积铜层。 元件的组装包括：抛光意图接触的铜层的表面，使得它们具有小于1nm RMS的粗糙度和亲水性，使表面接触，并将结构储存在大气压和 环境温度。

公开(公告)号：US09508684B2

公开(公告)日：2016-11-29

申请号：US15053267

申请日：2016-02-25

Applicant: SII Semiconductor Corporation

Inventor： Noriyuki Kimura

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L23/495 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81444 ,  H01L2224/83 ,  H01L2224/83001 ,  H01L2224/83005 ,  H01L2224/85 ,  H01L2224/85001 ,  H01L2224/85005 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: A first resin encapsulated body (25) and a second resin encapsulated body (26) are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated body (25) includes: a first semiconductor element (2); an external terminal (5); inner wiring (4); and a first resin (6) for covering those components, at least a rear surface of the external terminal (5), a rear surface of the semiconductor element (2), and a surface of the inner wiring (4) are exposed from the first resin (6). The second resin encapsulated body (26) includes: a second semiconductor element (7) having an electrode pad formed on a surface thereof; a second resin (8) for covering the second semiconductor element; and a metal body connected to the electrode pad, and is partly exposed from the second resin. The inner wiring and the metal body are electrically connected to each other.

Abstract translation: 堆叠第一树脂封装体（25）和第二树脂封装体（26）以形成树脂封装的半导体器件。 第一树脂封装体（25）包括：第一半导体元件（2）; 外部终端（5）; 内部接线（4）; 以及用于覆盖这些部件的第一树脂（6），至少外部端子（5）的后表面，半导体元件（2）的后表面和内部布线（4）的表面从 第一树脂（6）。 第二树脂封装体（26）包括：第二半导体元件（7），其表面上形成有电极焊盘; 用于覆盖第二半导体元件的第二树脂（8） 和连接到电极焊盘的金属体，并且部分地从第二树脂露出。 内部布线和金属体彼此电连接。

公开(公告)号：US09502370B2

公开(公告)日：2016-11-22

申请号：US15040861

申请日：2016-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuei-Sung Chang ,  Nien-Tsung Tsai ,  Ting-Hau Wu ,  Yi Heng Tsai

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/29 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05082 ,  H01L2224/26145 ,  H01L2224/2745 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29193 ,  H01L2224/32506 ,  H01L2224/83097 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00012

Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.

Abstract translation: 提供一种用于接合半导体器件的系统和方法。 一个实施方案包括通过以栅格图案提供其中一种反应物的附加材料来停止共晶粘合材料的流动，使得当共晶材料流入附加材料时，附加材料将改变流动共晶材料的组成 并使材料固化，从而停止流动。 其他实施例提供了额外的布局以将附加材料放入流动共晶材料的路径中。

公开(公告)号：US20160322327A1

公开(公告)日：2016-11-03

申请号：US14959139

申请日：2015-12-04

Applicant: Mitsubishi Electric Corporation

Inventor： Yasunari HINO ,  Daisuke KAWABATA

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/2711 ,  H01L2224/27334 ,  H01L2224/27505 ,  H01L2224/27848 ,  H01L2224/29013 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29294 ,  H01L2224/29347 ,  H01L2224/2957 ,  H01L2224/2969 ,  H01L2224/32054 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/82203 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2224/83986 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor clement. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film.

Abstract translation: 根据本发明的半导体器件的制造方法包括：（a）在基板（绝缘基板）上设置具有片状且具有烧结性的接合材料; （b）在（a）之后，在所述接合材料上设置半导体元件; 和（c）在对基板和半导体元件之间的接合材料施加压力的同时烧结接合材料。 接合材料包括Ag或Cu的颗粒，并且颗粒被有机膜涂覆。

公开(公告)号：US09418954B2

公开(公告)日：2016-08-16

申请号：US14659680

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/3213 ,  H01L21/56 ,  H01L21/768 ,  H01L23/36 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract translation: 一种装置包括组装在插入器上的芯片。 电绝缘层在芯片周围涂覆插入件的上表面。 第一金属线在插入件的上表面上延伸并且布置在与芯片连接的导电元件之间。 每个第一金属线的端部被布置成延伸超过芯片在插入件上的投影。 导热通孔将第一金属线的端部连接到支撑在设备的上表面处的散热器。

公开(公告)号：US09406577B2

公开(公告)日：2016-08-02

申请号：US14201935

申请日：2014-03-10

Applicant: GLOBAL FOUNDRIES Singapore Pte. Ltd.

Inventor： Ranjan Rajoo ,  Kai Chong Chan

IPC: H01L23/10 ,  B81C3/00 ,  H01L21/50 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/10 ,  B81C3/001 ,  H01L21/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/2761 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29078 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/30505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8389 ,  H01L2224/83905 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.

Abstract translation: 公开了一种半导体晶片堆叠和形成半导体器件的方法。 该方法包括向第一和第二晶片提供顶表面和底表面。 晶片包括边缘和非边缘区域，并且第一晶片包括形成在非边缘区域中的器件。 可以在第一晶片的边缘区域形成第一保护密封。 第一和第二晶片可以进一步结合以形成器件堆叠。 装置堆叠中的保护密封件接触第一和第二晶片以形成密封，并且在随后的处理中保护装置。