公开(公告)号：US11799012B2

公开(公告)日：2023-10-24

申请号：US17012088

申请日：2020-09-04

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H10B12/00 ,  H01L21/285

CPC分类号： H01L29/4941 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/3213 ,  H01L29/42372 ,  H10B12/05 ,  H10B12/482 ,  H01L21/28518 ,  H01L21/28556 ,  H10B12/30

摘要： A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20230335592A1

公开(公告)日：2023-10-19

申请号：US18331917

申请日：2023-06-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sung-Li WANG ,  Mrunal A. KHADERBAD ,  Yasutoshi OKUNO

IPC分类号： H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417 ,  H01L29/165

CPC分类号： H01L29/0847 ,  H01L29/45 ,  H01L23/535 ,  H01L27/0924 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/76883 ,  H01L21/76802 ,  H01L21/76876 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/76224 ,  H01L21/0262 ,  H01L21/28518 ,  H01L29/665 ,  H01L21/76897 ,  H01L29/41725 ,  H01L29/165 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02164 ,  H01L29/6653 ,  H01L21/31116

摘要： A semiconductor device includes first and second semiconductor fins extending from a substrate, and first and second epitaxial layers wrapping around the first and second semiconductor fins, respectively. The semiconductor device further includes a contact plug over the first epitaxial layer and the second epitaxial layer. The contact plug includes a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer. The first and second interfacial layers include a noble metal element and a Group IV element.

公开(公告)号：US20230317812A1

公开(公告)日：2023-10-05

申请号：US18172347

申请日：2023-02-22

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takashi YOSHIMURA ,  Makoto SHIMOSAWA ,  Motoyoshi KUBOUCHI ,  Misaki UCHIDA

IPC分类号： H01L29/45 ,  H01L27/06 ,  H01L29/32 ,  H01L29/40 ,  H01L29/739 ,  H01L21/22 ,  H01L21/285

CPC分类号： H01L29/45 ,  H01L27/0664 ,  H01L29/32 ,  H01L29/407 ,  H01L29/7397 ,  H01L21/221 ,  H01L21/28518

摘要： Provided is a semiconductor device including a MOS gate structure provided in a semiconductor substrate, including: an interlayer dielectric film which includes a contact hole and is provided above the semiconductor substrate; a conductive first barrier metal layer provided on side walls of the interlayer dielectric film in the contact hole; a conductive second barrier metal layer stacked on the first barrier metal layer in the contact hole; and a silicide layer provided on an upper surface of the semiconductor substrate below the contact hole, in which the first barrier metal layer is more dense than the second barrier metal layer, and a film thickness thereof is 1 nm or more and 10 nm or less.

公开(公告)号：US11764225B2

公开(公告)日：2023-09-19

申请号：US17344391

申请日：2021-06-10

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Anthony K. Stamper ,  Uzma Rana ,  Siva P. Adusumilli ,  Steven M. Shank

IPC分类号： H01L27/12 ,  H01L29/45 ,  H01L21/84 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49

CPC分类号： H01L27/1203 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/84 ,  H01L29/45 ,  H01L29/4933

摘要： The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

公开(公告)号：US11749603B2

公开(公告)日：2023-09-05

申请号：US17811649

申请日：2022-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/3065 ,  H01L23/528

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/485 ,  H01L23/528 ,  H01L23/535 ,  H01L23/53266 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/7848

摘要： A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

公开(公告)号：US20230260792A1

公开(公告)日：2023-08-17

申请号：US18304059

申请日：2023-04-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin Hsiang TSENG ,  Chi-Ruei YEH ,  Tsung-Yu CHIANG

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/32133 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

公开(公告)号：US11690227B2

公开(公告)日：2023-06-27

申请号：US17323819

申请日：2021-05-18

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  James Pak ,  Unsoon Kim ,  Inkuk Kang ,  Sung-Taeg Kang ,  Kuo Tung Chang

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H10B43/40 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35 ,  H01L29/45 ,  H01L29/51

CPC分类号： H10B43/40 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35 ,  H01L29/517

摘要： A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.

公开(公告)号：US20230197805A1

公开(公告)日：2023-06-22

申请号：US18108890

申请日：2023-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shahaji B. MORE ,  Jia-Ying MA ,  Cheng-Han LEE

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/285

CPC分类号： H01L29/41791 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823871 ,  H01L29/66545 ,  H01L21/28518

摘要： A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

公开(公告)号：US20230170397A1

公开(公告)日：2023-06-01

申请号：US18103306

申请日：2023-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Ming HSU ,  Pei-Yu CHOU ,  Chih-Pin TSAO ,  Kuang-Yuan HSU ,  Jyh-Huei CHEN

IPC分类号： H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/45 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823418 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L29/665 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76855

摘要： A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

公开(公告)号：US11664439B2

公开(公告)日：2023-05-30

申请号：US17243476

申请日：2021-04-28

申请人： Intel Corporation

发明人： Subhash M. Joshi ,  Jeffrey S. Leib ,  Michael L. Hattendorf

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.