公开(公告)号：US20150318851A1

公开(公告)日：2015-11-05

申请号：US14654127

申请日：2013-12-12

申请人： GAN SYSTEMS INC.

发明人： John ROBERTS ,  Greg P. KLOWAK

IPC分类号： H03K17/687

CPC分类号： H03K17/687 ,  H01F19/08 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/1204 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

摘要翻译： 公开了一种包括用于功率晶体管的驱动电路的电子开关系统和装置，其特别适用于MOSFET驱动的常规氮化镓（GaN）功率晶体管。 优选地，具有集成的低电压横向MOSFET驱动器的低功率，高速CMOS驱动器电路以混合共源共栅布置串联耦合到高电压GaN HEMT，并且提供对噪声和电压瞬变的改进的控制。 监控和控制功能，包括闭锁和钳位，都是基于对关闭和启动调节的Vcc条件进行监控，以实现更安全的操作，特别是对于高电压和高电流开关。 优选实施例还提供具有减小的输入损耗的隔离，自供电的高速驱动器件。

公开(公告)号：US09171797B2

公开(公告)日：2015-10-27

申请号：US13910786

申请日：2013-06-05

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Robert C. Frye

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L21/50 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H05K1/16 ,  H01L21/56 ,  H01L23/31 ,  H05K3/20 ,  H05K3/28 ,  H05K3/46

CPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

摘要翻译： 半导体器件具有衬底，形成在衬底上的第一钝化层和形成在衬底上的集成无源器件。 集成无源器件可以包括电感器，电容器和电阻器。 在该集成无源器件上形成第二钝化层。 系统组件被安装到第二钝化层并电连接到第二导电层。 在整合的无源器件上形成模具化合物。 模具化合物的热膨胀系数近似等于系统组分的热膨胀系数。 去除衬底。 将一个开口蚀刻到第一钝化层中，并且将焊料凸块沉积在第一钝化层中的开口上，以电连接到集成的无源器件。 可以在模制化合物或第一钝化层上形成金属层以进行屏蔽。

公开(公告)号：US09171784B2

公开(公告)日：2015-10-27

申请号：US13759831

申请日：2013-02-05

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Dan Clavette

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H02M3/158 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/84

摘要： A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

摘要翻译： 公开了一种双功率转换器封装。 该封装包括引线框架，其具有构造成支撑第一控制FET的漏极的第一控制FET栅极和被配置为支撑第二控制PET的漏极的第二控制FET栅极。 引线框还包括配置成支持第一同步FET的源极和第二同步FET的源的同步FET栅极，以及配置成接收每个控制PETS和每个同步FET的控制信号的第一多个触点 从引线框架外部的驱动器集成电路（IC）。 引线框架可以另外包括第一和第二开关节点，其被配置用于经由第一夹子电连接到第一控制FET和第一同步FET，并且分别经由第二夹子连接到第二控制PET和第二同步PET。

公开(公告)号：US09153686B2

公开(公告)日：2015-10-06

申请号：US14340198

申请日：2014-07-24

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L23/34 ,  H01L29/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H02M7/00 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在其间插入形成区域SDR。

公开(公告)号：US20150279791A1

公开(公告)日：2015-10-01

申请号：US14618328

申请日：2015-02-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Keiju YAMADA

IPC分类号： H01L23/66 ,  H01L23/64 ,  H01L23/498

CPC分类号： H01L23/645 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/206

摘要： According to one embodiment, a semiconductor device includes a part or entirety of a switching power supply, at least one semiconductor element, and at least one line composed of a inner conductor and a soft magnetic member sheathing the inner conductor. The semiconductor device further includes, for example, a circuit substrate on which the part or entirety of the switching power supply and the semiconductor elements are mounted. The lines are mounted on the circuit substrate.

摘要翻译： 根据一个实施例，半导体器件包括开关电源的一部分或全部，至少一个半导体元件，以及由内部导体和包围内部导体的软磁性构件组成的至少一条线。 半导体器件还包括例如其上安装有开关电源和半导体元件的一部分或全部的电路基板。 线路安装在电路基板上。

公开(公告)号：US20150270198A1

公开(公告)日：2015-09-24

申请号：US14658479

申请日：2015-03-16

申请人： NXP B.V.

发明人： Vittorio Cuoco ,  Albert van Zuijlen ,  Josephus van der Zanden

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/13 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit arrangement comprising a substrate and a flange disposed on top of the substrate. The flange comprises a cantilever portion configured to project over the substrate. A die disposed on top of the flange. A first output terminal disposed on the substrate. A first lead configured to provide for an electrical connection between the die and the first output terminal. A first electrically conducting member configured to provide at least part of a current return path between the substrate and the die and arranged to bridge a gap between the cantilever portion and the substrate. The first electrically conducting member is disposed between the die and the first output terminal and is configured to enable electrical current to flow from the substrate to the cantilever portion of the flange.

摘要翻译： 一种集成电路装置，包括衬底和布置在衬底顶部上的凸缘。 凸缘包括构造成突出在基板上的悬臂部分。 设置在凸缘顶部的模具。 布置在基板上的第一输出端子。 第一引线，被配置为提供管芯和第一输出端子之间的电连接。 第一导电构件，其构造成在所述基板和所述管芯之间提供至少一部分电流返回路径，并布置成桥接所述悬臂部分和所述基板之间的间隙。 第一导电构件设置在管芯和第一输出端子之间，并且构造成使得电流能够从衬底流到凸缘的悬臂部分。

公开(公告)号：US20150270186A1

公开(公告)日：2015-09-24

申请号：US14566503

申请日：2014-12-10

申请人： Mitsubishi Electric Corporation

发明人： Masaomi MIYAZAWA ,  Mituharu TABATA ,  Takuya TAKAHASHI

IPC分类号： H01L23/053 ,  H01L23/16

CPC分类号： H01L23/053 ,  H01L23/16 ,  H01L24/36 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/40137 ,  H01L2224/84205 ,  H01L2924/00014 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/37099

摘要： An electrode includes an extending portion extending such that both ends thereof get into a first recessed portion and a second recessed portion provided in a first inner wall and a second inner wall, respectively, facing each other in a lateral direction of a case. The extent to which both the ends of the extending portion get into is set such that positions of both the ends thereof in a case where both the ends are narrowed toward a midpoint therebetween to reduce a length of the extending portion to 70% of the length of the extending portion exist between positions of the first and second inner walls in a case where the first and second inner walls are each narrowed toward a midpoint therebetween by 10% of the distance between the first and second inner walls.

摘要翻译： 电极包括延伸部分，其延伸使得其两端分别设置在第一内壁和第二内壁中的第一凹部和第二内壁中，第一内壁和第二内壁在壳体的横向方向上彼此面对。 延伸部的两端部进入的程度被设定为使得两端的两端在其两端之间的中点变窄的情况下的两端的位置，以将延伸部的长度缩短至长度的70％ 在第一内壁和第二内壁各自朝向中间点变窄的情况下，在第一和第二内壁之间的距离的10％的情况下，第一和第二内壁的位置之间存在延伸部分。

公开(公告)号：US09142534B2

公开(公告)日：2015-09-22

申请号：US13148544

申请日：2009-10-13

申请人： Chao-Hsing Chen ,  Schang-Jing Hon ,  Alexander Chan Wang ,  Li-Tian Liang ,  Chin-Yung Fan ,  Chien-Kai Chung ,  Min-Hsun Hsieh

发明人： Chao-Hsing Chen ,  Schang-Jing Hon ,  Alexander Chan Wang ,  Li-Tian Liang ,  Chin-Yung Fan ,  Chien-Kai Chung ,  Min-Hsun Hsieh

IPC分类号： H01L27/15 ,  H01L27/02 ,  H01L25/065 ,  H01L25/075 ,  H01L27/32 ,  H01L33/62

CPC分类号： H01L27/15 ,  H01L25/0753 ,  H01L27/153 ,  H01L27/156 ,  H01L27/3211 ,  H01L33/50 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/8592 ,  H01L2924/12032 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A light-emitting device is provided that is capable of being directly connected to an alternative current source, including at least one electronic element; at least one light-emitting diode array chip; at least one bonding pad, a conductive trace, and a submount for supporting the electronic element, the light-emitting diode array chip, the bonding pad, and the conductive trace. The conductive trace is electrically connected to the electronic element, the light-emitting diode array chip, and bonding pad.

摘要翻译： 提供了能够直接连接到包括至少一个电子元件的替代电流源的发光器件; 至少一个发光二极管阵列芯片; 至少一个接合焊盘，导电迹线和用于支撑电子元件的基座，发光二极管阵列芯片，接合焊盘和导电迹线。 导电迹线电连接到电子元件，发光二极管阵列芯片和接合焊盘。

公开(公告)号：US20150255455A1

公开(公告)日：2015-09-10

申请号：US14720121

申请日：2015-05-22

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Takamitsu KANAZAWA ,  Satoru AKIYAMA

IPC分类号： H01L27/088 ,  H02P27/06 ,  H03K17/567 ,  H01L27/098 ,  H03K3/012

CPC分类号： H01L27/0883 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02P27/06 ,  H03K3/012 ,  H03K17/102 ,  H03K17/107 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00014 ,  H01L2924/00

摘要： There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state.

摘要翻译： 存在配置有级联耦合的通常的JFET和常关MOSFET的半导体器件可能由于错误导通等而断裂的可能性。半导体器件配置有常导SiCJFET和常关 Si型MOSFET。 常闭SiCJFET和常关Si型MOSFET级联耦合并配置开关电路。 根据一个输入信号，常控SiCJFET和常关Si型MOSFET被控制为具有两个晶体管被设置为截止状态的周期。

公开(公告)号：US20150255442A1

公开(公告)日：2015-09-10

申请号：US14336890

申请日：2014-07-21

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hiroshi Matsuyama

IPC分类号： H01L25/18 ,  H01L23/538 ,  H01L23/522 ,  H01L29/739 ,  H01L29/861

CPC分类号： H01L25/18 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L25/065 ,  H01L25/072 ,  H01L2224/451 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

摘要： According to one embodiment, a power semiconductor module includes a substrate, a first interconnection layer, semiconductor elements, and a rectifier element. The first interconnection layer is provided on the substrate. The semiconductor elements are provided on the first interconnection layer. Each of the semiconductor elements includes first, second, and third electrodes. The second electrode is electrically connected to the first interconnection layer. The rectifier element is provided on the first interconnection layer, and includes a fifth electrode electrically connected to the first interconnection layer and a fourth electrode electrically connected to the first electrode. The semiconductor elements and the rectifier elements are radially disposed on the first interconnection layer. Arbitrary points fallen in respective regions of the semiconductor elements and an arbitrary point fallen in a region of the rectifier element are disposed in point symmetry or line symmetry based on the first point.

摘要翻译： 根据一个实施例，功率半导体模块包括衬底，第一互连层，半导体元件和整流元件。 第一互连层设置在基板上。 半导体元件设置在第一互连层上。 每个半导体元件包括第一，第二和第三电极。 第二电极电连接到第一互连层。 整流元件设置在第一互连层上，并且包括电连接到第一互连层的第五电极和与第一电极电连接的第四电极。 半导体元件和整流元件径向设置在第一互连层上。 任意点落在半导体元件的各个区域中，并且在整流元件的区域中下降的任意点基于第一点设置为点对称或线对称。