公开(公告)号：US20160093594A1

公开(公告)日：2016-03-31

申请号：US14863894

申请日：2015-09-24

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

Abstract translation: 半导体器件包括形成在陶瓷衬底上的多个金属图案和安装在多个金属图案中的一些上的半导体芯片。 此外，在多个金属图案的周边部分中形成多个中空部分。 此外，多个中空部分不形成在与多个金属图案中的半导体芯片重叠的区域中。 此外，多个中空部分设置在多个金属图案中，多个金属图案布置在多个金属图案中最靠近陶瓷基板的顶表面的周边部分的位置。

公开(公告)号：US20130335134A1

公开(公告)日：2013-12-19

申请号：US13909293

申请日：2013-06-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamitsu KANAZAWA ,  Satoru AKIYAMA

IPC: H01L27/088 ,  H03K3/012 ,  H01L29/16

CPC classification number: H01L27/0883 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02P27/06 ,  H03K3/012 ,  H03K17/102 ,  H03K17/107 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

Abstract translation: 存在配置有级联耦合的通常的JFET和常关MOSFET的半导体器件可能由于错误导通等而断裂的可能性。半导体器件配置有常导SiCJFET和常关 Si型MOSFET。 常闭SiCJFET和常关Si型MOSFET级联耦合并配置开关电路。 根据一个输入信号，常控SiCJFET和常关Si型MOSFET被控制成具有将两个晶体管设置在OFF状态的周期。

公开(公告)号：US20160163615A1

公开(公告)日：2016-06-09

申请号：US14941721

申请日：2015-11-16

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro MITAMURA ,  Koji BANDO ,  Yukihiro SATO ,  Takamitsu KANAZAWA

IPC: H01L23/36 ,  H02M7/537 ,  H01L29/861 ,  H01L23/31 ,  H01L27/06 ,  H01L29/739

CPC classification number: H02M7/537 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/0781 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H02M7/003 ,  H02P27/06 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014

Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

Abstract translation: 例如，半导体器件具有连接到其上安装有作为热源的半导体芯片的芯片安装部的第二部分的引线和连接到芯片安装部的第三部分的引线，半导体芯片上的半导体芯片 作为热源安装。 此外，每个引线具有从密封构件突出的突出部分。 以这种方式，可以提高半导体器件的散热特性。

公开(公告)号：US20170263587A1

公开(公告)日：2017-09-14

申请号：US15609242

申请日：2017-05-31

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Katsuhiko FUNATSU ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/049 ,  H01L23/498 ,  H01L25/07 ,  H01L23/24 ,  H01L23/373 ,  H01L25/16 ,  H01L25/18 ,  H02M7/219

CPC classification number: H01L25/0655 ,  H01L21/4846 ,  H01L23/049 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/0905 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/16251 ,  H01L2924/181 ,  H02M7/219 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

公开(公告)号：US20170033710A1

公开(公告)日：2017-02-02

申请号：US15194624

申请日：2016-06-28

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Koji BANDO ,  Takamitsu KANAZAWA ,  Ryo KANDA ,  Akihiro TAMURA ,  Hirobumi MINEGISHI

IPC: H02M7/537 ,  H03K17/567 ,  H01L23/495 ,  H01L23/04 ,  H01L27/06 ,  H02M7/00

CPC classification number: H02M7/537 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/49541 ,  H01L27/0664 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H02M7/003 ,  H02M7/53875 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

Abstract translation: 提高了半导体器件的可靠性。 其上形成有控制电路的第三半导体芯片，并且多个IGBT芯片的第一半导体芯片经由高侧继电器板电连接。 也就是说，第一半导体芯片和第三半导体芯片经由第一线，高侧继电器板和第二线电连接。 类似地，其上形成有控制电路的第三半导体芯片和多个IGBT芯片的第二半导体芯片经由低侧继电器板电连接。 也就是说，第二半导体芯片和第三半导体芯片经由第一线，低侧继电器板和第二线电连接。

公开(公告)号：US20150255455A1

公开(公告)日：2015-09-10

申请号：US14720121

申请日：2015-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamitsu KANAZAWA ,  Satoru AKIYAMA

IPC: H01L27/088 ,  H02P27/06 ,  H03K17/567 ,  H01L27/098 ,  H03K3/012

CPC classification number: H01L27/0883 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02P27/06 ,  H03K3/012 ,  H03K17/102 ,  H03K17/107 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state.

Abstract translation: 存在配置有级联耦合的通常的JFET和常关MOSFET的半导体器件可能由于错误导通等而断裂的可能性。半导体器件配置有常导SiCJFET和常关 Si型MOSFET。 常闭SiCJFET和常关Si型MOSFET级联耦合并配置开关电路。 根据一个输入信号，常控SiCJFET和常关Si型MOSFET被控制为具有两个晶体管被设置为截止状态的周期。

公开(公告)号：US20180138828A1

公开(公告)日：2018-05-17

申请号：US15867978

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Koji BANDO ,  Takamitsu KANAZAWA ,  Ryo KANDA ,  Akihiro TAMURA ,  Hirobumi MINEGISHI

IPC: H02M7/537 ,  H01L23/04 ,  H02M7/00 ,  H01L27/06

CPC classification number: H02M7/537 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/49541 ,  H01L27/0664 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H02M7/003 ,  H02M7/53875 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

公开(公告)号：US20180122727A1

公开(公告)日：2018-05-03

申请号：US15858493

申请日：2017-12-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro SATO ,  Akira MUTO ,  Ryo KANDA ,  Takamitsu KANAZAWA

IPC: H01L23/495 ,  H01L29/739 ,  H01L23/31 ,  H01L25/075 ,  H01L27/06 ,  H02P27/06

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

公开(公告)号：US20170141086A1

公开(公告)日：2017-05-18

申请号：US15420410

申请日：2017-01-31

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/07 ,  H01L23/10 ,  H01L23/00 ,  H01L29/417 ,  H01L21/54 ,  H01L23/16 ,  H01L23/498 ,  H01L23/053 ,  H01L21/52

CPC classification number: H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

公开(公告)号：US20170033035A1

公开(公告)日：2017-02-02

申请号：US15174568

申请日：2016-06-06

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Akira MUTO ,  Ryo KANDA ,  Takamitsu KANAZAWA

IPC: H01L23/495 ,  H01L29/739 ,  H01L27/06 ,  H01L23/31

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

Abstract translation: 提高半导体器件的可靠性。 芯片安装部TAB5布置成向+ x方向侧移动。 此外，半导体芯片CHP1（LV）的栅电极焊盘和半导体芯片CHP3的焊盘通过导线W1a和导线W1b通过继电器引线RL1电耦合。 同样地，半导体芯片CHP1（LW）的栅电极焊盘和半导体芯片CHP3的焊盘通过引线W1c和引线W1d通过继电器引线RL2电耦合。 此时，从密封体MR露出的继电器引线RL1，RL2的部分的结构与作为密封体MR的多个引线LD1，LD2的密封体MR露出的各部分的结构不同 外部端子。