公开(公告)号：US20170263587A1

公开(公告)日：2017-09-14

申请号：US15609242

申请日：2017-05-31

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Katsuhiko FUNATSU ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/049 ,  H01L23/498 ,  H01L25/07 ,  H01L23/24 ,  H01L23/373 ,  H01L25/16 ,  H01L25/18 ,  H02M7/219

CPC classification number: H01L25/0655 ,  H01L21/4846 ,  H01L23/049 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/0905 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/16251 ,  H01L2924/181 ,  H02M7/219 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

公开(公告)号：US20160148859A1

公开(公告)日：2016-05-26

申请号：US14862102

申请日：2015-09-22

Applicant: Renesas Electronics Corporation

Inventor： Akira MUTO ,  Koji BANDO ,  Yukihiro SATO ,  Kazuhiro MITAMURA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49575 ,  B60L3/003 ,  B60L11/1803 ,  B60L15/007 ,  B60L2220/12 ,  B60L2240/525 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49565 ,  H01L23/544 ,  H01L23/564 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29116 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40998 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/77704 ,  H01L2224/78704 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/84136 ,  H01L2224/84138 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/84862 ,  H01L2224/8585 ,  H01L2224/92147 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  Y02T10/645 ,  Y02T10/7005 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05559 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

Abstract translation: 假设在引线框架中设置一对悬挂部件，并且夹子包括主体部分和一对延伸部分，所述一对延伸部分被安装并支撑在所述一对悬挂部分上。 因此，夹子安装在一个引线（一点）上，一对悬挂部分（两点）和夹子被三个点支撑。

公开(公告)号：US20160043042A1

公开(公告)日：2016-02-11

申请号：US14919597

申请日：2015-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Yuichi YATO ,  Tomoaki UNO

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/564 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

公开(公告)号：US20130147064A1

公开(公告)日：2013-06-13

申请号：US13764336

申请日：2013-02-11

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Tomoaki UNO

IPC: H01L23/492

CPC classification number: H01L23/492 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The reliability of a semiconductor device is improved.A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Abstract translation: 提高了半导体器件的可靠性。 半导体器件的封装在内部包括形成功率MOSFET的第一半导体芯片和第二半导体芯片以及形成控制第一和第二半导体芯片的控制电路的第三半导体芯片。 第一至第三半导体芯片分别安装在芯片焊盘上。 第一半导体芯片的高侧的源电极接合焊盘通过金属板与管芯焊盘的第一管芯焊盘电连接。 在芯片焊盘7D2的顶面设置有形成在安装有第二半导体芯片的区域中的镀层和形成在金属板接合的区域中的另一个镀层，并且将镀层彼此分离，并且用 在其间不形成镀层的区域。

公开(公告)号：US20180315684A1

公开(公告)日：2018-11-01

申请号：US15934310

申请日：2018-03-23

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Toshinori KIYOHARA

IPC: H01L23/495

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

公开(公告)号：US20160163615A1

公开(公告)日：2016-06-09

申请号：US14941721

申请日：2015-11-16

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro MITAMURA ,  Koji BANDO ,  Yukihiro SATO ,  Takamitsu KANAZAWA

IPC: H01L23/36 ,  H02M7/537 ,  H01L29/861 ,  H01L23/31 ,  H01L27/06 ,  H01L29/739

CPC classification number: H02M7/537 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/0781 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H02M7/003 ,  H02P27/06 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014

Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

Abstract translation: 例如，半导体器件具有连接到其上安装有作为热源的半导体芯片的芯片安装部的第二部分的引线和连接到芯片安装部的第三部分的引线，半导体芯片上的半导体芯片 作为热源安装。 此外，每个引线具有从密封构件突出的突出部分。 以这种方式，可以提高半导体器件的散热特性。

公开(公告)号：US20130043576A1

公开(公告)日：2013-02-21

申请号：US13655446

申请日：2012-10-19

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki NAKAMURA ,  Atsushi FUJIKI ,  Tatsuhiro SEKI ,  Nobuya KOIKE ,  Yukihiro SATO ,  Kisho ASHIDA

IPC: H01L23/495

CPC classification number: H01L27/07 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/66 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.

Abstract translation: 提高半导体器件的性能和可靠性。 对于半导体芯片CP1，用于开关的功率MOSFET Q1和Q2，用于检测功率MOSFET Q1的发热的二极管DD1，用于检测功率MOSFET Q2的发热的二极管DD2和多个焊盘电极PD 。 功率MOSFET Q1和二极管DD1布置在侧面SD1侧的第一MOSFET区域RG1中，功率MOSFET Q2和二极管DD2布置在侧面SD2侧的第二MOSFET区RG2中。 二极管DD1沿着侧面SD1配置，二极管DD2沿着侧面SD2配置，除了用于源极的焊盘电极PDS1和PDS2以外的所有焊盘电极PD沿着二极管DD1和DD2之间的侧面SD3排列。

公开(公告)号：US20170103940A1

公开(公告)日：2017-04-13

申请号：US15385637

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Akira MUTO ,  Koji BANDO ,  Yukihiro SATO ,  Kazuhiro MITAMURA

IPC: H01L23/495 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L23/49575 ,  B60L3/003 ,  B60L11/1803 ,  B60L15/007 ,  B60L2220/12 ,  B60L2240/525 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49565 ,  H01L23/544 ,  H01L23/564 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29116 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40998 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/77704 ,  H01L2224/78704 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/84136 ,  H01L2224/84138 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/84862 ,  H01L2224/8585 ,  H01L2224/92147 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  Y02T10/645 ,  Y02T10/7005 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05559 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

公开(公告)号：US20160233204A1

公开(公告)日：2016-08-11

申请号：US15133032

申请日：2016-04-19

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko FUNATSU ,  Tomoaki UNO ,  Toru UEGURI ,  Yukihiro SATO

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the leadframe, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

Abstract translation: 为了提高将带施加到基板的后表面上的带的可靠性，同时确保施加到基板的后表面的带的耐热性。 在支撑构件中设置的沟槽的底表面和驱动器IC芯片的上表面之间存在间隙。 另一方面，引线框架的上表面侧由支撑构件支撑，使得沟槽的底表面接触安装在低MOS芯片上的低MOS片的上表面。 因此，即使在驱动IC芯片和Low-MOS芯片安装在引线框架的上表面侧的状态下，也可以将带子可靠地施加到引线框架的后表面（特别是到后表面 的产品区域）。

公开(公告)号：US20160093594A1

公开(公告)日：2016-03-31

申请号：US14863894

申请日：2015-09-24

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

Abstract translation: 半导体器件包括形成在陶瓷衬底上的多个金属图案和安装在多个金属图案中的一些上的半导体芯片。 此外，在多个金属图案的周边部分中形成多个中空部分。 此外，多个中空部分不形成在与多个金属图案中的半导体芯片重叠的区域中。 此外，多个中空部分设置在多个金属图案中，多个金属图案布置在多个金属图案中最靠近陶瓷基板的顶表面的周边部分的位置。