公开(公告)号：US20240006532A1

公开(公告)日：2024-01-04

申请号：US18465050

申请日：2023-09-11

Applicant: Acorn Semi, LLC

Inventor： Paul A. Clifton ,  Andreas Goebel

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/7849 ,  H01L29/0649 ,  H01L27/1203 ,  H01L21/76283 ,  H01L21/02381 ,  H01L21/76254 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7846 ,  H01L29/105

Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

公开(公告)号：US20230420516A1

公开(公告)日：2023-12-28

申请号：US18464839

申请日：2023-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ka-Hing FUNG

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/41791 ,  H01L29/66803 ,  H01L29/6656 ,  H01L21/823431 ,  H01L29/7851 ,  H01L29/7848

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another, a source/drain feature adjacent to the plurality of nanostructures, and an inner spacer layer. The inner spacer layer includes a vertical portion interposing between the plurality of nanostructures and the source/drain feature and a plurality of horizontal portions interposing between the nanostructures. A source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance.

公开(公告)号：US11855210B2

公开(公告)日：2023-12-26

申请号：US17671042

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/76 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0262 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/1608

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

公开(公告)号：US11855208B2

公开(公告)日：2023-12-26

申请号：US16898659

申请日：2020-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Tsai ,  Shahaji B. More ,  Cheng-Yi Peng ,  Yu-Ming Lin ,  Kuo-Feng Yu ,  Ziwei Fang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L21/027 ,  H01L29/161 ,  H01L29/36 ,  H01L29/165 ,  H01L21/3105

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/0274 ,  H01L21/31053 ,  H01L29/161 ,  H01L29/36

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

公开(公告)号：US11854898B2

公开(公告)日：2023-12-26

申请号：US17322007

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/78 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/1608 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

公开(公告)号：US11854787B2

公开(公告)日：2023-12-26

申请号：US17735006

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53238 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20230387303A1

公开(公告)日：2023-11-30

申请号：US18446435

申请日：2023-08-08

Applicant: Peking University ,  Beijing Intellectual Property Operation Management Co., LTD

Inventor： Ming LI ,  Ran BI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823885 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/66545 ,  H01L29/78642 ,  H01L21/823814 ,  H01L21/823878

Abstract: A method for fabricating a vertical channel nanowire transistor with asymmetric stress distribution includes: (A) growing epitaxially a single-crystal material on a substrate; forming a laminate of a bottom source-drain material and a channel material; and generating a vertical uniaxial stress in the lightly-doped channel layer; (B) forming an inter-device isolation in an active layer; (C) forming a vertical channel by patterning; (D) depositing a dielectric layer to form a bottom gate isolation; (E) depositing a dummy gate layer followed by patterning to form a dummy gate pattern; (F) depositing a dielectric layer to form a top gate isolation; (G) patterning the top gate isolation; and forming a top source-drain by epitaxy growth; (H) removing a dummy gate; and forming a gate oxide layer and a metal gate; and (I) forming metal contact at individual ends of the device.

公开(公告)号：US20230387125A1

公开(公告)日：2023-11-30

申请号：US18362862

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lien HUANG ,  Che-Ming HSU ,  Ching-Feng FU ,  Huan-Just LIN

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/0924 ,  H01L21/823468 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L21/823481 ,  H01L21/823475 ,  H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2221/1063

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

公开(公告)号：US11799015B2

公开(公告)日：2023-10-24

申请号：US17703884

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20230335643A1

公开(公告)日：2023-10-19

申请号：US18338736

申请日：2023-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Che TSAI ,  Min-Yann HSIEH ,  Hua-Feng CHEN ,  Kuo-Hua PAN

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/165 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.