公开(公告)号：US11605623B2

公开(公告)日：2023-03-14

申请号：US16457699

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Eungnak Han ,  Paul A. Nyhus ,  Florian Gstrein ,  Richard E. Schenker

IPC: H01L27/02 ,  C08L33/12 ,  C08L25/06 ,  C08L53/00

Abstract: An integrated circuit structure includes an active region containing more active semiconductor devices, wherein the active region comprises a first grating of metal and dielectric materials with only vertically aligned structures thereon. A transition region containing inactive structures is adjacent to the active region, wherein the transition region comprises a second grating of metal and dielectric materials having at least one of vertical aligned structures and vertical random structures thereon. Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon.

公开(公告)号：US20220102148A1

公开(公告)日：2022-03-31

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US10991599B2

公开(公告)日：2021-04-27

申请号：US16390922

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Paul A. Nyhus

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/48 ,  H01L23/498 ,  H01L21/764 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

公开(公告)号：US20190393170A1

公开(公告)日：2019-12-26

申请号：US16017409

申请日：2018-06-25

Applicant: INTEL CORPORATION

Inventor： Paul A. Nyhus ,  Gurpreet Singh

IPC: H01L23/58 ,  H01L23/31 ,  H01L21/768 ,  H01L29/34

Abstract: A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.

公开(公告)号：US10319625B2

公开(公告)日：2019-06-11

申请号：US15772711

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Mohit K. Haran ,  Charles H. Wallace ,  Robert M. Bigwood ,  Deepak S. Rao ,  Alexander F. Kaplan

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

公开(公告)号：US09666451B2

公开(公告)日：2017-05-30

申请号：US14914095

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Paul A. Nyhus

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/48 ,  H01L21/768 ,  H01L21/764 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/764 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

公开(公告)号：US11373950B2

公开(公告)日：2022-06-28

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US10892223B2

公开(公告)日：2021-01-12

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US10559529B2

公开(公告)日：2020-02-11

申请号：US16069154

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Leonard P. Guler ,  Manish Chandhok ,  Paul A. Nyhus

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.

公开(公告)号：US10459338B2

公开(公告)日：2019-10-29

申请号：US15480208

申请日：2017-04-05

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Eungnak Han ,  Swaminathan Sivakumar ,  Ernisse S. Putna

IPC: G03F7/039 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/768 ,  G03F7/00 ,  G03F7/004 ,  G03F7/038 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/3205 ,  H01L21/3213 ,  B81C1/00

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.