公开(公告)号：US12199161B2

公开(公告)日：2025-01-14

申请号：US17123677

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Mohit K. Haran ,  Andy Chih-Hung Wei

IPC: H01L29/423 ,  H01L27/088

Abstract: Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.

公开(公告)号：US20240249946A1

公开(公告)日：2024-07-25

申请号：US18625348

申请日：2024-04-03

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US11990472B2

公开(公告)日：2024-05-21

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Michael K. Harper ,  William Hsu ,  Biswajeet Guha ,  Tahir Ghani ,  Niels Zussblatt ,  Jeffrey Miles Tan ,  Benjamin Kriegel ,  Mohit K. Haran ,  Reken Patel ,  Oleg Golonzka ,  Mohammad Hasan

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US12080639B2

公开(公告)日：2024-09-03

申请号：US16579077

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Manish Chandhok ,  Richard E. Schenker ,  Florian Gstrein ,  Leonard P. Guler ,  Charles H. Wallace ,  Paul A. Nyhus ,  Curtis Ward ,  Mohit K. Haran ,  Reken Patel

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/66

CPC classification number: H01L23/5226 ,  H01L21/02175 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/66 ,  H01L2223/6677

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

公开(公告)号：US20240113177A1

公开(公告)日：2024-04-04

申请号：US17957887

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Quan Shi ,  Marni Nabors ,  Charles H. Wallace ,  Xinning Wang ,  Tahir Ghani ,  Andy Chih-Hung Wei ,  Mohit K. Haran ,  Leonard P. Guler ,  Sivakumar Venkataraman ,  Reken Patel ,  Richard Schenker

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.

公开(公告)号：US11664274B2

公开(公告)日：2023-05-30

申请号：US16421184

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Mohit K. Haran ,  Gopinath Bhimarasetti

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/033 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283

Abstract: Embodiments disclosed herein include edge placement error mitigation processes and structures fabricated with such processes. In an embodiment, a method of fabricating an interconnect layer over a semiconductor die comprises forming a patterned layer over a substrate, disposing a resist layer over the patterned layer and patterning the resist layer to expose portions of the patterned layer. In an embodiment, overlay misalignment during the patterning results in the formation of edge placement error openings. In an embodiment, the method further comprises correcting the edge placement error openings, and patterning an opening into the substrate after correcting edge placement error openings.

公开(公告)号：US11211324B2

公开(公告)日：2021-12-28

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US12154855B2

公开(公告)日：2024-11-26

申请号：US16579088

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Reken Patel ,  Richard E. Schenker ,  Charles H. Wallace

IPC: H01L23/528 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02

Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.

公开(公告)号：US11652045B2

公开(公告)日：2023-05-16

申请号：US17511656

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/5329

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20230079586A1

公开(公告)日：2023-03-16

申请号：US17473431

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Mohammad Hasan ,  Tahir Ghani ,  Pratik A. Patel ,  Leonard P. Guler ,  Mohit K. Haran ,  Clifford L. Ong

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.