公开(公告)号：US11990472B2

公开(公告)日：2024-05-21

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Michael K. Harper ,  William Hsu ,  Biswajeet Guha ,  Tahir Ghani ,  Niels Zussblatt ,  Jeffrey Miles Tan ,  Benjamin Kriegel ,  Mohit K. Haran ,  Reken Patel ,  Oleg Golonzka ,  Mohammad Hasan

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.