Invention Grant
- Patent Title: Contact over active gate structures with metal oxide layers to inhibit shorting
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Application No.: US16579077Application Date: 2019-09-23
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Publication No.: US12080639B2Publication Date: 2024-09-03
- Inventor: Rami Hourani , Manish Chandhok , Richard E. Schenker , Florian Gstrein , Leonard P. Guler , Charles H. Wallace , Paul A. Nyhus , Curtis Ward , Mohit K. Haran , Reken Patel
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L21/02 ; H01L21/768 ; H01L23/522 ; H01L23/66

Abstract:
Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.
Public/Granted literature
- US20210090990A1 CONTACT OVER ACTIVE GATE STRUCTURES WITH METAL OXIDE LAYERS TO INHIBIT SHORTING Public/Granted day:2021-03-25
Information query
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