公开(公告)号：US20170018531A1

公开(公告)日：2017-01-19

申请号：US14799756

申请日：2015-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC分类号： H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L23/50 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

摘要翻译： 采用集成式封装架构的封装架构，以及参考通道，以提供延伸通过InFO-POP架构的参考电压。 如果需要，可以暴露参考通孔，然后连接到可用于屏蔽InFO-POP体系结构的屏蔽涂层。 参考通孔可以通过使用一个或多个分割工艺暴露参考通道的顶表面或侧壁来暴露。

公开(公告)号：US09548279B2

公开(公告)日：2017-01-17

申请号：US14466493

申请日：2014-08-22

申请人： Kabushiki Kaisha Toshiba

发明人： Atsuko Iida ,  Tadahiro Sasaki ,  Nobuto Managaki ,  Yutaka Onozuka ,  Hiroshi Yamada

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L23/04 ,  H01L23/60 ,  H05K1/11 ,  H05K3/40

CPC分类号： H01L23/49827 ,  H01L23/04 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/60 ,  H01L23/66 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/24195 ,  H01L2224/82106 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2924/15788 ,  H01L2924/19105 ,  H01P1/20 ,  H01P1/2005 ,  H01P1/202 ,  H01P5/028 ,  H05K1/117 ,  H05K3/403 ,  H05K2201/0919 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079

摘要： A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

摘要翻译： 根据实施例的连接构件包括电介质材料，穿透介电材料的穿透通孔，设置在介电材料中的第一金属平面，第一金属平面垂直于穿透通孔的延伸方向，第一金属平面 穿过穿透孔的第二金属平面和与穿透通孔的延伸方向平行地设置在电介质材料上的第二金属平面，连接到第一金属平面的第二金属平面。

公开(公告)号：US09543373B2

公开(公告)日：2017-01-10

申请号：US14061615

申请日：2013-10-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Wei Liang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Ching-Feng Yang ,  Ming-Kai Liu ,  Chia-Chun Miao

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L49/02 ,  H01L25/065 ,  H01L23/488 ,  H01L21/48 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46 ,  H01L23/522 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/522 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/065 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2224/80815 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/92124 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/186 ,  H05K3/4682 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/01047 ,  H01L2924/01029

摘要： A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

摘要翻译： 半导体结构包括包括第一半导体管芯和第二半导体管芯的三维堆叠。 第二半导体管芯与第一半导体管芯在第一半导体管芯和第二半导体管芯之间具有凸块连接。 半导体结构包括在第一半导体管芯和第二半导体管芯之间的模制化合物。 金属结构的第一部分在三维堆叠的表面上并且接触第二半导体管芯的背面和金属结构的第二部分在三维堆叠的表面上，并且被配置为将三维堆叠与 外部电子设备。

公开(公告)号：US20170005056A1

公开(公告)日：2017-01-05

申请号：US15266752

申请日：2016-09-15

申请人： Apple Inc.

发明人： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

摘要翻译： 为层叠半导体存储器封装提供了系统和方法。 每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。 每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

公开(公告)号：US09536862B2

公开(公告)日：2017-01-03

申请号：US14980996

申请日：2015-12-28

申请人： Invensas Corporation

发明人： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L21/52 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

摘要翻译： 半导体集成电路（110）或组件至少部分地设置在两个插入件（120）之间的空腔中。 导电通孔（204M）通过至少一个插入件或至少穿过插入器的衬底，并到达半导体集成电路或组件。 其他导电通孔（204M.1）至少部分地通过多个插入件并且连接到到达或者电容耦合到半导体IC或组件的导电通孔。 还提供其他功能。

公开(公告)号：US20160379956A1

公开(公告)日：2016-12-29

申请号：US15258933

申请日：2016-09-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L21/78 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/31 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/78 ,  H01L21/786 ,  H01L21/84 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/19

摘要： A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric layers, e.g., the polymer layers, of the redistribution layers are removed along the scribe line such that after singulation the dielectric layers are recessed back from the edges of the die. The corner regions may be recessed further. The recessed regions may be triangular, rounded, or other shape. In some embodiments one or more of the corner regions may be recessed further relative to the remaining corner regions. The redistribution layers may be recessed along one or both of the front side redistribution layers and the backside redistribution layers.

公开(公告)号：US09530857B2

公开(公告)日：2016-12-27

申请号：US10560717

申请日：2004-06-11

申请人： Freddy Roozeboom ,  Adrianus Alphonsus Jozef Buijsman ,  Patrice Gamand ,  Antonius Lucien Adrianus Maria Kemmeren ,  Gerardus Tarcisius Maria Hubert

发明人： Freddy Roozeboom ,  Adrianus Alphonsus Jozef Buijsman ,  Patrice Gamand ,  Antonius Lucien Adrianus Maria Kemmeren ,  Gerardus Tarcisius Maria Hubert

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L29/66 ,  H01L21/768 ,  H01L23/48 ,  H01L27/08 ,  H01L29/06

CPC分类号： H01L23/66 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49872 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/0657 ,  H01L29/66181 ,  H01L2223/6622 ,  H01L2223/6666 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on the other side of the substrate.

摘要翻译： 半导体衬底包括垂直互连和具有公共电介质层的垂直电容器。 衬底可以适当地与另外的装置组合以形成组件。 衬底可以在包括一侧的第一步骤，然后在衬底的另一侧上的第二步骤的蚀刻处理中制成。

公开(公告)号：US20160365335A1

公开(公告)日：2016-12-15

申请号：US15247259

申请日：2016-08-25

申请人： Bryan Black ,  Michael Z. Su ,  Gamal Refai-Ahmed ,  Joe Siegel ,  Seth Prejean

发明人： Bryan Black ,  Michael Z. Su ,  Gamal Refai-Ahmed ,  Joe Siegel ,  Seth Prejean

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05095 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/17181 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

摘要翻译： 公开了一种具有导电孔的半导体芯片及其制造方法。 该方法包括在第一半导体芯片的层中形成第一多个导电通孔。 第一多个导电通孔包括第一端和第二端。 第一导体焊盘与第一多个导电通孔的第一端欧姆接触形成。

公开(公告)号：US20160365302A1

公开(公告)日：2016-12-15

申请号：US15248726

申请日：2016-08-26

申请人： Invensas Corporation

发明人： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh ,  Belgacem Haba

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/04

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

摘要： A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

摘要翻译： 制造组件的方法可以包括形成限定前表面和后表面的电路结构，以及在后表面上形成衬底。 电路结构的形成可以包括形成耦合到载体的第一介电层。 第一电介质层可以包括构造成与一个或多个微电子元件的触点和第一迹线接合的前触点。 电路结构的形成可以包括通过第一迹线在与前触点耦合的后表面处形成后导电元件。 基板的形成可以包括直接在后表面上形成电介质元件。 电介质元件可以具有面向后导电元件并与其连接的第一导电元件。 电介质元件可以包括与第一导电元件耦合的第二迹线。 基板的形成可以包括在基板的表面上形成端子。

公开(公告)号：US20160358833A1

公开(公告)日：2016-12-08

申请号：US15163016

申请日：2016-05-24

申请人： SHIN-ETSU CHEMICAL CO., LTD.

发明人： Kyoko SOGA ,  Satoshi ASAI ,  Katsuya TAKEMURA

IPC分类号： H01L23/29 ,  H01L25/00 ,  G03F7/075 ,  G03F7/20 ,  G03F7/40 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L23/296 ,  C08G59/3281 ,  C08G59/621 ,  C08G77/52 ,  C08G77/60 ,  C08K5/13 ,  C08L63/00 ,  C09D183/14 ,  C09D183/16 ,  G03F7/0757 ,  G03F7/20 ,  G03F7/40 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/18162 ,  C08L83/10

摘要： The present invention is a semiconductor apparatus including a semiconductor device, an on-semiconductor-device metal pad and a metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first photosensitive insulating layer formed on the semiconductor device, and a second photosensitive insulating layer formed on the first photosensitive insulating layer, in which the first and second photosensitive insulating layers are composed of a photo-curable resin composition containing a silicone polymer compound having an epoxy group-containing repeating unit shown by formula (1) and a phenolic hydroxyl group-containing repeating unit shown by formula (2), a photosensitive acid generator, a solvent, and crosslinking agents. There can be provided a semiconductor apparatus that can be easily placed on a circuit board and stacked by forming a fine electrode on the semiconductor device and providing a through electrode outside the semiconductor device.

摘要翻译： 本发明是一种半导体装置，包括半导体器件金属焊盘和与半导体器件电连接的金属互连，每个电连接到金属互连的通孔电极和焊料凸块，第一光敏元件 形成在半导体器件上的绝缘层，以及形成在第一感光绝缘层上的第二感光绝缘层，其中第一和第二感光绝缘层由光固化性树脂组合物构成，该组合物含有具有环氧基的重复 由式（1）表示的单元和式（2）所示的含酚羟基的重复单元，光敏酸产生剂，溶剂和交联剂。 可以提供一种半导体装置，其可以容易地放置在电路板上并通过在半导体器件上形成精细电极并在半导体器件外部提供通孔来堆叠。