公开(公告)号：US09252127B1

公开(公告)日：2016-02-02

申请号：US14328380

申请日：2014-07-10

申请人： Invensas Corporation

发明人： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/538 ,  H01L21/98 ,  H01L21/50 ,  H01L21/67 ,  H01L25/065 ,  H01L23/00 ,  H01L21/52

CPC分类号： H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

摘要翻译： 半导体集成电路（110）或组件至少部分地设置在两个插入件（120）之间的空腔中。 导电通孔（204M）通过至少一个插入件或至少穿过插入器的衬底，并到达半导体集成电路或组件。 其他导电通孔（204M.1）至少部分地通过多个插入件并且连接到到达或者电容耦合到半导体IC或组件的导电通孔。 还提供其他功能。

公开(公告)号：US20140138846A1

公开(公告)日：2014-05-22

申请号：US14075089

申请日：2013-11-08

申请人： Nthdegree Technologies Worldwide Inc.

发明人： Richard A. Blanchard ,  William J. Ray ,  Mark D. Lowenthal ,  Xiaorong Cai

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/288

CPC分类号： H01L23/481 ,  H01L21/288 ,  H01L21/486 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5328 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0332 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08165 ,  H01L2224/73265 ,  H01L2224/76155 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2224/80 ,  H01L2924/00

摘要： Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgassing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.

摘要翻译： 通孔（孔）形成在晶片或电介质层中。 包含微观金属颗粒的低粘度导电油墨沉积在晶片的顶表面上以覆盖通孔。 施加外力以将油墨推入通孔中，包括用于使过孔中的空气排气的电力，磁力，离心力，真空或吸力。 表面上的任何剩余的油墨都被刮刀，纺丝，气刀或下面的光致抗蚀剂层除去。 将通孔中的油墨加热以蒸发液体并烧结剩余的金属颗粒，以在通孔中形成导电路径。 所得到的晶片可以结合到一个或多个其它晶片并且被单个化以形成3-D模块。

公开(公告)号：US11694950B2

公开(公告)日：2023-07-04

申请号：US17198653

申请日：2021-03-11

申请人： Powertech Technology Inc.

发明人： Chih-Yen Su ,  Chun-Te Lin

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/08165 ,  H01L2224/32225

摘要： A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

公开(公告)号：US09543270B1

公开(公告)日：2017-01-10

申请号：US14814524

申请日：2015-07-31

申请人： Inotera Memories, Inc.

发明人： Shih-Fan Kuan ,  Yi-Jen Lo

IPC分类号： H01L25/04 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L23/5386 ,  H01L21/52 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/823475 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/525 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/08238 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/1434 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.

摘要翻译： 多器件封装包括衬底，至少两个器件区域，第一再分布层，外部芯片，多个第一连接器和导电触点。 两个器件区域由衬底形成，并且衬底具有与第一表面相对的第一表面和第二表面。 第一再分配层设置在第一表面上并电连接到两个器件区域，并且外部芯片设置在第一再分配层上。 第一连接器插入在第一再分配层和外部芯片之间以互连第一再分配层和外部芯片，并且导电接触从第二表面延伸到基板的第一表面以电连接器件区域。

公开(公告)号：US09496198B2

公开(公告)日：2016-11-15

申请号：US14499222

申请日：2014-09-28

申请人： Texas Instruments Incorporated

发明人： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Hiep Nguyen ,  Darvin Edwards

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC分类号： H01L23/373 ,  H01L21/4871 ,  H01L21/4889 ,  H01L23/367 ,  H01L23/3675 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/03416 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05193 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/05693 ,  H01L2224/08165 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01006 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2224/45099 ,  H01L2224/03

摘要： A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

摘要翻译： 微电子器件包括在半导体器件的前表面处具有部件的半导体器件和在半导体器件的背面上的背面散热器层。 背面散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US20240014138A1

公开(公告)日：2024-01-11

申请号：US18139862

申请日：2023-04-26

申请人： Intel Corporation

发明人： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H05K1/11 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L23/49816 ,  H01L24/08 ,  H05K1/111 ,  H01L23/49822 ,  H01L25/0655 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/08146 ,  H01L2224/08165 ,  H01L2924/014

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US11749746B2

公开(公告)日：2023-09-05

申请号：US17244293

申请日：2021-04-29

申请人： QUALCOMM Incorporated

发明人： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC分类号： H01L29/737 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L29/205 ,  H01L29/66

CPC分类号： H01L29/7371 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/08 ,  H01L24/80 ,  H01L29/205 ,  H01L29/66318 ,  H01L2224/08165 ,  H01L2224/80001

摘要： In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

公开(公告)号：US09105628B1

公开(公告)日：2015-08-11

申请号：US13434688

申请日：2012-03-29

申请人： Valery Dubin

发明人： Valery Dubin

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/538

CPC分类号： H01L23/49827 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/486 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5384 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1461 ,  H01L2924/00

摘要： Through substrate via (TSuV) structures and method of making the same are disclosed herein. In embodiments, TSuV structures are metal filled selectively to avoid forming significant metal overburden on non-via surfaces of the substrate. In certain embodiments, post-fill metal removal/planarization operations are eliminated for reduced process complexity and manufacturing cost. In embodiments, selective metal fill entails selective electroless or electrolytic deposition. Both front side and back side selective deposition methods are described along with features of through substrate via structures made with such methods.

摘要翻译： 通过衬底通孔（TSuV）结构及其制备方法在此公开。 在实施例中，TSuV结构被选择性地金属填充以避免在衬底的非通孔表面上形成显着的金属覆盖层。 在某些实施例中，消除后填充金属去除/平面化操作以降低工艺复杂性和制造成本。 在实施例中，选择性金属填充需要选择性化学镀或电解沉积。 还描述了前侧和后侧选择性沉积方法以及通过这种方法制成的通过基底通孔结构的特征。

公开(公告)号：US20140231986A1

公开(公告)日：2014-08-21

申请号：US14260064

申请日：2014-04-23

申请人： Valery Dubin

发明人： Valery Dubin

IPC分类号： B81B7/00 ,  H01L23/498

CPC分类号： H01L23/49827 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/486 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5384 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1461 ,  H01L2924/00

摘要： Through substrate via (TSuV) structures and method of making the same are disclosed herein. In embodiments, TSuV structures are metal filled selectively to avoid forming significant metal overburden on non-via surfaces of the substrate. In certain embodiments, post-fill metal removal/planarization operations are eliminated for reduced process complexity and manufacturing cost. In embodiments, selective metal fill entails selective electroless or electrolytic deposition. Both front side and back side selective deposition methods are described along with features of through substrate via structures made with such methods.

摘要翻译： 通过衬底通孔（TSuV）结构及其制备方法在此公开。 在实施例中，TSuV结构被选择性地金属填充以避免在衬底的非通孔表面上形成显着的金属覆盖层。 在某些实施例中，消除后填充金属去除/平面化操作以降低工艺复杂性和制造成本。 在实施例中，选择性金属填充需要选择性化学镀或电解沉积。 还描述了前侧和后侧选择性沉积方法以及通过这种方法制成的通过基底通孔结构的特征。

公开(公告)号：US20070108595A1

公开(公告)日：2007-05-17

申请号：US11274139

申请日：2005-11-16

申请人： Gamal Refai-Ahmed

发明人： Gamal Refai-Ahmed

IPC分类号： H01L23/34

CPC分类号： H01L23/367 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/38 ,  H01L23/427 ,  H01L24/19 ,  H01L2224/08165 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor device includes a die, a substrate, a heat spreader and a plurality of signal interconnects extending from the die. The heat spreader has a base and a plurality of fins. The heat spreader is mounted on the substrate in such a way that the base of the head spreader is in thermal communication with the die. The fins protrude downwardly into the substrate conducting heat away from the die and into the substrate.

摘要翻译： 半导体器件包括管芯，衬底，散热器和从管芯延伸的多个信号互连。 散热器具有基部和多个翅片。 散热器以这样的方式安装在基板上，使得喷头的底部与模具热连通。 翅片向下突出到基板中，导热离开模具并进入基板。