公开(公告)号：US11362055B2

公开(公告)日：2022-06-14

申请号：US17096190

申请日：2020-11-12

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/00

Abstract: The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

公开(公告)号：US10950557B2

公开(公告)日：2021-03-16

申请号：US16780921

申请日：2020-02-04

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

公开(公告)号：US20170287870A1

公开(公告)日：2017-10-05

申请号：US15455149

申请日：2017-03-10

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/14 ,  H01L2924/1438 ,  H01L2924/3025

Abstract: A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. The second chip is disposed on the first chip and exposes the first pads. The pillar bumps are respectively disposed on a plurality of second pads of the second chips. The encapsulant encapsulates the first chip and the second chip and exposes a top surface of each second stud bump. The first conductive vias penetrate the encapsulant and connect the first stud bumps. Each first conductive via covers the rough surface of each first stud bump.

公开(公告)号：US20200321259A1

公开(公告)日：2020-10-08

申请号：US16417671

申请日：2019-05-21

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor package structure includes a substrate, a chip, and an encapsulant. The chip is disposed on the substrate. The encapsulant is disposed on the substrate and covers the chip. The encapsulant has a top surface away from the substrate and at least one protruding strip protruding from the top surface.

公开(公告)号：US10276510B2

公开(公告)日：2019-04-30

申请号：US15713717

申请日：2017-09-25

Applicant: Powertech Technology Inc.

Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

IPC: H01L21/56 ,  H01L23/552 ,  H01L23/00

Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

公开(公告)号：US20220148955A1

公开(公告)日：2022-05-12

申请号：US17198653

申请日：2021-03-11

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen SU ,  Chun-Te Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

公开(公告)号：US11302539B2

公开(公告)日：2022-04-12

申请号：US16987470

申请日：2020-08-07

Applicant: Powertech Technology Inc.

Inventor： Tsung-Han Chiang ,  Chun-Te Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683

Abstract: A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.

公开(公告)号：US20190096821A1

公开(公告)日：2019-03-28

申请号：US15713717

申请日：2017-09-25

Applicant: Powertech Technology Inc.

Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56

Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

公开(公告)号：US20170287874A1

公开(公告)日：2017-10-05

申请号：US15455143

申请日：2017-03-10

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82039 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/15192 ,  H01L2924/3025

Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

公开(公告)号：US11694950B2

公开(公告)日：2023-07-04

申请号：US17198653

申请日：2021-03-11

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/08165 ,  H01L2224/32225

Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.